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Groups > linux.kernel > #1379843
| From | Laxman Dewangan <ldewangan@nvidia.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads |
| Date | 2016-04-15 16:20 +0200 |
| Message-ID | <rocLf-4gd-1@gated-at.bofh.it> (permalink) |
| References | (4 earlier) <ro8eC-Nk-5@gated-at.bofh.it> <ro8Rk-1jQ-11@gated-at.bofh.it> <ro9X4-25i-15@gated-at.bofh.it> <roazL-2oI-3@gated-at.bofh.it> <rocBB-4b6-15@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Friday 15 April 2016 07:33 PM, Linus Walleij wrote: > On Fri, Apr 15, 2016 at 1:47 PM, Laxman Dewangan <ldewangan@nvidia.com> wrote: >> On Friday 15 April 2016 04:45 PM, Linus Walleij wrote: >>> On Fri, Apr 15, 2016 at 11:55 AM, Laxman Dewangan <ldewangan@nvidia.com> >>> wrote: >>> But to be sure we would like to know what is actually happening, >>> electronically speaking, when you set this up. Do you have any >>> idea? >> From electronic point of view, the value of VIL, VIH, VOL, VOH (Input/output >> voltage level for low and high state) are different when talking for 0 t >> 1.8V and 0 to 3.3V. > Yeah that I get. But since it is switched on a per-pin basis, and > this is not about what voltage is actually supplied to the I/O cell, > because that comes from the outside, it is a mystery why it is > even needed. > > I understand that there is a bit selecting driving voltage level in > the register range, what I don't understand is what that is > doing in the I/O cell. > > The bit in the register must be routed to somehing in the I/O cell > and I would like to know what. I take it that an ordinary CMOS > totem-pole push-pull output is going to work the same with 1.8 > and 3.3V alike so it's obviously not enabling any extra transistors > or anything. > > I dont have answer for this now and I need to discuss with HW team to get this info. I will be back here after discussion with HW team.
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[PATCH 0/7] pinctrl: soc/tegra: Add support to configure IO rail voltage and pad power states Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
[PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Thierry Reding <thierry.reding@gmail.com> - 2016-04-12 17:30 +0200
Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 19:20 +0200
Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 20:10 +0200
Re: [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Jon Hunter <jonathanh@nvidia.com> - 2016-04-12 20:10 +0200
[PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-13 11:10 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-13 11:20 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-13 11:40 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 16:20 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 16:30 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 17:20 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 17:30 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 17:50 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 19:00 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 19:50 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 20:10 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Jon Hunter <jonathanh@nvidia.com> - 2016-04-15 20:40 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 21:00 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Stephen Warren <swarren@wwwdotorg.org> - 2016-04-15 18:40 +0200
Re: [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 18:50 +0200
[PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 10:10 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 11:00 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 11:30 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 12:10 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 13:20 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 14:00 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 16:10 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-15 16:20 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-19 12:10 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-26 15:50 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Stephen Warren <swarren@wwwdotorg.org> - 2016-04-26 17:40 +0200
Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Stephen Warren <swarren@wwwdotorg.org> - 2016-04-15 18:40 +0200
[PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field definition Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 17:20 +0200
Re: [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field definition Thierry Reding <thierry.reding@gmail.com> - 2016-04-12 17:30 +0200
Re: [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field definition Laxman Dewangan <ldewangan@nvidia.com> - 2016-04-12 19:10 +0200
Re: [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field definition Linus Walleij <linus.walleij@linaro.org> - 2016-04-15 09:50 +0200
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