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[PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock

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As of an earlier change in this series ("Documentation: mmc:
sdhci-of-arasan: Add ability to export card clock") the SDHCI driver
used on Rockchip SoCs can now expose its clock.  Let's now specify that
the PHY can use it.

Letting the PHY get access to this clock means it can adjust
phyctrl_frqsel field appropriately.  Although the Rockchip PHY appears
slightly different than the reference Arasan one, you can see that the
Arasan datasheet [1] had it defined as:
  Select the frequency range of DLL operation:
  3b'000 => 200MHz to 170 MHz
  3b'001 => 170MHz to 140 MHz
  3b'010 => 140MHz to 110 MHz
  3b'011 => 110MHz to 80MHz
  3b'100 => 80MHz to 50 MHz
  3b'101 => 275Mhz to 250MHz
  3b'110 => 250MHz to 225MHz
  3b'111 => 225MHz to 200MHz

On the Rockchip version of the PHY we have less granularity but the idea
is the same.

[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf

Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
 Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
index 555cb0f40690..fd118b071e5e 100644
--- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
+++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
@@ -7,6 +7,11 @@ Required properties:
  - reg: PHY register address offset and length in "general
    register files"
 
+Optional clocks (see ../clock/clock-bindings.txt), specified by name:
+ - emmcclk: The card clock exported by the SDHCI driver.  Although this is
+	    listed as optional (because most boards can get basic functionality
+	    without having access to it), it is strongly suggested.
+
 Example:
 
 
@@ -20,6 +25,8 @@ grf: syscon@ff770000 {
 	emmcphy: phy@f780 {
 		compatible = "rockchip,rk3399-emmc-phy";
 		reg = <0xf780 0x20>;
+		clocks = <&sdhci>;
+		clock-names = "emmcclk";
 		#phy-cells = <0>;
 	};
 };
-- 
2.8.0.rc3.226.g39d4020

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[PATCH 0/11] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
    Re: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability  to export card clock Rob Herring <robh@kernel.org> - 2016-06-08 22:20 +0200
      Re: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to  export card clock Doug Anderson <dianders@chromium.org> - 2016-06-08 23:00 +0200
        Re: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability  to export card clock Rob Herring <robh@kernel.org> - 2016-06-10 15:20 +0200
  [PATCH 05/11] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 01/11] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 10/11] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_off() Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 09/11] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
    Re: [PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get  an exported card clock Rob Herring <robh@kernel.org> - 2016-06-10 15:40 +0200
  [PATCH 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200

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