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[PATCH 01/11] phy: rockchip-emmc: Increase lock time allowance

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Previous PHY code waited a fixed amount of time for the DLL to lock at
power on time.  Unfortunately, the time for the DLL to lock is actually
a bit more dynamic and can be longer if the card clock is slower.

Instead of waiting a fixed 30 us, let's now dynamically wait until the
lock bit gets set.  We'll wait up to 10 ms which should be OK even if
the card clock is at the super slow 100 kHz.

On its own, this change makes the PHY power on code a little more
robust.  Before this change the PHY was relying on the eMMC code to make
sure the PHY was only powered on when the card clock was set to at least
50 MHz before, though this reliance wasn't documented anywhere.

This change will be even more useful in future changes where we actually
need to be able to wait for a DLL lock at slower clock speeds.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
 drivers/phy/phy-rockchip-emmc.c | 27 +++++++++++++++++++--------
 1 file changed, 19 insertions(+), 8 deletions(-)

diff --git a/drivers/phy/phy-rockchip-emmc.c b/drivers/phy/phy-rockchip-emmc.c
index a69f53630e67..8336053aea5c 100644
--- a/drivers/phy/phy-rockchip-emmc.c
+++ b/drivers/phy/phy-rockchip-emmc.c
@@ -85,6 +85,7 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
 {
 	unsigned int caldone;
 	unsigned int dllrdy;
+	unsigned long timeout;
 
 	/*
 	 * Keep phyctrl_pdb and phyctrl_endll low to allow
@@ -137,15 +138,25 @@ static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
 				   PHYCTRL_ENDLL_MASK,
 				   PHYCTRL_ENDLL_SHIFT));
 	/*
-	 * After enable analog DLL circuits, we need an extra 10.2us
-	 * for dll to be ready for work. But according to testing, we
-	 * find some chips need more than 25us.
+	 * After enabling analog DLL circuits docs say that we need 10.2 us if
+	 * our source clock is at 50 MHz and that lock time scales linearly
+	 * with clock speed.  If we are powering on the PHY and the card clock
+	 * is super slow (like 100 kHZ) this could take as long as 5.1 ms.
+	 * Hopefully we won't be running at 100 kHz, but we should still make
+	 * sure we wait long enough.
 	 */
-	udelay(30);
-	regmap_read(rk_phy->reg_base,
-		    rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
-		    &dllrdy);
-	dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
+	timeout = jiffies + msecs_to_jiffies(10);
+	do {
+		udelay(1);
+
+		regmap_read(rk_phy->reg_base,
+			rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
+			&dllrdy);
+		dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
+		if (dllrdy == PHYCTRL_DLLRDY_DONE)
+			break;
+	} while (!time_after(jiffies, timeout));
+
 	if (dllrdy != PHYCTRL_DLLRDY_DONE) {
 		pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
 		return -ETIMEDOUT;
-- 
2.8.0.rc3.226.g39d4020

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[PATCH 0/11] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
    Re: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability  to export card clock Rob Herring <robh@kernel.org> - 2016-06-08 22:20 +0200
      Re: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to  export card clock Doug Anderson <dianders@chromium.org> - 2016-06-08 23:00 +0200
        Re: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability  to export card clock Rob Herring <robh@kernel.org> - 2016-06-10 15:20 +0200
  [PATCH 05/11] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 01/11] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 10/11] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_off() Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 09/11] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
  [PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
    Re: [PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get  an exported card clock Rob Herring <robh@kernel.org> - 2016-06-10 15:40 +0200
  [PATCH 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200

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