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Groups > linux.kernel > #1416695
| From | Douglas Anderson <dianders@chromium.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock |
| Date | 2016-06-08 00:50 +0200 |
| Message-ID | <rHxYR-aA-15@gated-at.bofh.it> (permalink) |
| References | <rHxYR-aA-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work
with arasan,sdhci-5.1) need to know the card clock in order to function
properly. Let's expose this clock using a standard device tree
mechanism so that the PHY can get access to and query the card clock.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
---
Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index b67e623ca1ff..074d03e630ec 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -30,6 +30,12 @@ Optional Properties:
- arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
used to access core corecfg registers. Offsets of registers in this
syscon are determined based on the main compatible string for the device.
+ - clock-output-names: If specified, this will be the name of the card clock
+ which will be exposed by this device. Required if #clock-cells is
+ specified.
+ - #clock-cells: If specified this should be the value <0>. With this property
+ in place we will export a clock representing the Card Clock. This clock
+ is expected to be consumed by our PHY. You must also specify
Example:
sdhci@e0100000 {
@@ -61,7 +67,9 @@ Example:
arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
+ clock-output-names = "emmc_cardclock";
phys = <&emmc_phy>;
phy-names = "phy_arasan";
+ #clock-cells = <0>;
status = "disabled";
};
--
2.8.0.rc3.226.g39d4020
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[PATCH 0/11] Changes to support 150 MHz eMMC on rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
[PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
Re: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Rob Herring <robh@kernel.org> - 2016-06-08 22:20 +0200
Re: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Doug Anderson <dianders@chromium.org> - 2016-06-08 23:00 +0200
Re: [PATCH 06/11] Documentation: mmc: sdhci-of-arasan: Add ability to export card clock Rob Herring <robh@kernel.org> - 2016-06-10 15:20 +0200
[PATCH 05/11] arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
[PATCH 01/11] phy: rockchip-emmc: Increase lock time allowance Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
[PATCH 10/11] phy: rockchip-emmc: Minor code cleanup in rockchip_emmc_phy_power_off() Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
[PATCH 09/11] phy: rockchip-emmc: Set phyctrl_frqsel based on card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
[PATCH 04/11] mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on rk3399 Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
[PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
Re: [PATCH 08/11] Documentation: phy: Let the rockchip eMMC PHY get an exported card clock Rob Herring <robh@kernel.org> - 2016-06-10 15:40 +0200
[PATCH 07/11] mmc: sdhci-of-arasan: Add ability to export card clock Douglas Anderson <dianders@chromium.org> - 2016-06-08 00:50 +0200
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