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Groups > linux.kernel > #1343241
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 |
| Date | 2016-02-25 16:00 +0100 |
| Message-ID | <r65yz-5kc-39@gated-at.bofh.it> (permalink) |
| References | <r65yy-5kc-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Add hwmod data for the eDMA blocks:
- TPCC: Third-party channel controller
- TPTC0: Third-party transfer controller 0
- TPTC1: Third-party transfer controller 1
The TPCC is following it's clock and power domain. This means that
the hwmod can not control it's status.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 88 +++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index b61355e2a771..3953ad031c43 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -430,6 +430,67 @@ static struct omap_hwmod dra7xx_dma_system_hwmod = {
};
/*
+ * 'tpcc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
+ .name = "tpcc",
+};
+
+static struct omap_hwmod dra7xx_tpcc_hwmod = {
+ .name = "tpcc",
+ .class = &dra7xx_tpcc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'tptc' class
+ *
+ */
+static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
+ .name = "tptc",
+};
+
+/* tptc0 */
+static struct omap_hwmod dra7xx_tptc0_hwmod = {
+ .name = "tptc0",
+ .class = &dra7xx_tptc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* tptc1 */
+static struct omap_hwmod dra7xx_tptc1_hwmod = {
+ .name = "tptc1",
+ .class = &dra7xx_tptc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
* 'dss' class
*
*/
@@ -2563,6 +2624,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l3_main_1 -> tpcc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_tpcc_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc0 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_tptc0_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
+/* l3_main_1 -> tptc1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_tptc1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU,
+};
+
static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
{
.name = "family",
@@ -3380,6 +3465,9 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l3_main_1__mcasp3,
&dra7xx_gmac__mdio,
&dra7xx_l4_cfg__dma_system,
+ &dra7xx_l3_main_1__tpcc,
+ &dra7xx_l3_main_1__tptc0,
+ &dra7xx_l3_main_1__tptc1,
&dra7xx_l3_main_1__dss,
&dra7xx_l3_main_1__dispc,
&dra7xx_l3_main_1__hdmi,
--
2.7.1
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[PATCH 00/11] ARM: DTS/clk: DRA7 family: enable eDMA and audio updates Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 03/11] ARM: DTS: dra7: Enable eDMA Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 11/11] ARM: DTS: dra7: Add nodes for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 05/11] ARM: DTS: dra7-evm: Enable AFIFO use for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 09/11] ARM: clk: dra7xx: Correct mcasp8_ahclkx_mux name Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 04/11] ARM: DTS: dra7: Use eDMA and add DAT port address for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 06/11] ARM: DTS: dra72-evm: Enable AFIFO use for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 01/11] ARM: DTS: dra7: Move the sDMA crossbar node under l4_cfg/scm Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 07/11] ARM: DTS: am57xx-beagle-x15: Move clkout2 source selection to codec node Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
Re: [PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 Paul Walmsley <paul@pwsan.com> - 2016-03-01 10:00 +0100
[PATCH 08/11] ARM: DTS: am57xx-beagle-x15: Enable AFIFO use for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Paul Walmsley <paul@pwsan.com> - 2016-03-01 10:20 +0100
Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-03-01 17:50 +0100
Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Paul Walmsley <paul@pwsan.com> - 2016-03-01 18:10 +0100
Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-03-03 12:20 +0100
Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Paul Walmsley <paul@pwsan.com> - 2016-03-03 16:40 +0100
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