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[PATCH 04/11] ARM: DTS: dra7: Use eDMA and add DAT port address for McASP3

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From: Misael Lopez Cruz <misael.lopez@ti.com>

McASP3 does not support constant addressing mode on the DAT
port, so increment transfers must be used instead.  This
restriction is also applicable for McASP1 and McASP2.

This DMA addressing constraint poses a major problem for sDMA
where constant addressing mode is used on the peripheral side.
Unfortunately, using increment transfers in sDMA comes with
important side effects.

The addressing mode used in eDMA is INC, so the silicon limitation
described above has no impact and the McASP3 DAT port can be
safely added by switching to eDMA instead of sDMA.

Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 arch/arm/boot/dts/dra7.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d2d2568b5695..258e6712a76b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1467,12 +1467,13 @@
 		mcasp3: mcasp@48468000 {
 			compatible = "ti,dra7-mcasp-audio";
 			ti,hwmods = "mcasp3";
-			reg = <0x48468000 0x2000>;
-			reg-names = "mpu";
+			reg = <0x48468000 0x2000>,
+			      <0x46000000 0x1000>;
+			reg-names = "mpu","dat";
 			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "tx", "rx";
-			dmas = <&sdma_xbar 133>, <&sdma_xbar 132>;
+			dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
 			dma-names = "tx", "rx";
 			clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
 			clock-names = "fck", "ahclkx";
-- 
2.7.1

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[PATCH 00/11] ARM: DTS/clk: DRA7 family: enable eDMA and audio updates Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
  [PATCH 03/11] ARM: DTS: dra7: Enable eDMA Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
  [PATCH 11/11] ARM: DTS: dra7: Add nodes for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
  [PATCH 05/11] ARM: DTS: dra7-evm: Enable AFIFO use for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
  [PATCH 09/11] ARM: clk: dra7xx: Correct mcasp8_ahclkx_mux name Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
  [PATCH 04/11] ARM: DTS: dra7: Use eDMA and add DAT port address for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
  [PATCH 06/11] ARM: DTS: dra72-evm: Enable AFIFO use for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
  [PATCH 01/11] ARM: DTS: dra7: Move the sDMA crossbar node under l4_cfg/scm Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
  [PATCH 07/11] ARM: DTS: am57xx-beagle-x15: Move clkout2 source selection to codec node Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
  [PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
    Re: [PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0,  tptc1 Paul Walmsley <paul@pwsan.com> - 2016-03-01 10:00 +0100
  [PATCH 08/11] ARM: DTS: am57xx-beagle-x15: Enable AFIFO use for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
  [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
    Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for  McASP1/2/4/5/6/7/8 Paul Walmsley <paul@pwsan.com> - 2016-03-01 10:20 +0100
      Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-03-01 17:50 +0100
        Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for  McASP1/2/4/5/6/7/8 Paul Walmsley <paul@pwsan.com> - 2016-03-01 18:10 +0100
          Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-03-03 12:20 +0100
            Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for  McASP1/2/4/5/6/7/8 Paul Walmsley <paul@pwsan.com> - 2016-03-03 16:40 +0100

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