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Groups > linux.kernel > #1343229
| From | Peter Ujfalusi <peter.ujfalusi@ti.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 11/11] ARM: DTS: dra7: Add nodes for McASP1/2/4/5/6/7/8 |
| Date | 2016-02-25 16:00 +0100 |
| Message-ID | <r65yz-5kc-23@gated-at.bofh.it> (permalink) |
| References | <r65yy-5kc-5@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Add nodes to represent all McASP ports in the dra7 family.
For system consistency use the eDMA for audio operations. sDMA would be
fine for 4/5/6/7/8 since their DAT port is not through L3 interconnect.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
arch/arm/boot/dts/dra7.dtsi | 112 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 112 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 258e6712a76b..700382093922 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1464,6 +1464,38 @@
status = "disabled";
};
+ mcasp1: mcasp@48460000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp1";
+ reg = <0x48460000 0x2000>,
+ <0x45800000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp2: mcasp@48464000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp2";
+ reg = <0x48464000 0x2000>,
+ <0x45c00000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
mcasp3: mcasp@48468000 {
compatible = "ti,dra7-mcasp-audio";
ti,hwmods = "mcasp3";
@@ -1480,6 +1512,86 @@
status = "disabled";
};
+ mcasp4: mcasp@4846c000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp4";
+ reg = <0x4846c000 0x2000>,
+ <0x48436000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp5: mcasp@48470000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp5";
+ reg = <0x48470000 0x2000>,
+ <0x4843a000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp6: mcasp@48474000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp6";
+ reg = <0x48474000 0x2000>,
+ <0x4844c000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp7: mcasp@48478000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp7";
+ reg = <0x48478000 0x2000>,
+ <0x48450000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
+ mcasp8: mcasp@4847c000 {
+ compatible = "ti,dra7-mcasp-audio";
+ ti,hwmods = "mcasp8";
+ reg = <0x4847c000 0x2000>,
+ <0x48454000 0x1000>;
+ reg-names = "mpu","dat";
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+ dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
+ dma-names = "tx", "rx";
+ clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
+ clock-names = "fck", "ahclkx";
+ status = "disabled";
+ };
+
crossbar_mpu: crossbar@4a002a48 {
compatible = "ti,irq-crossbar";
reg = <0x4a002a48 0x130>;
--
2.7.1
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[PATCH 00/11] ARM: DTS/clk: DRA7 family: enable eDMA and audio updates Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 03/11] ARM: DTS: dra7: Enable eDMA Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 11/11] ARM: DTS: dra7: Add nodes for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 05/11] ARM: DTS: dra7-evm: Enable AFIFO use for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 09/11] ARM: clk: dra7xx: Correct mcasp8_ahclkx_mux name Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 04/11] ARM: DTS: dra7: Use eDMA and add DAT port address for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 06/11] ARM: DTS: dra72-evm: Enable AFIFO use for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 01/11] ARM: DTS: dra7: Move the sDMA crossbar node under l4_cfg/scm Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 07/11] ARM: DTS: am57xx-beagle-x15: Move clkout2 source selection to codec node Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
Re: [PATCH 02/11] ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 Paul Walmsley <paul@pwsan.com> - 2016-03-01 10:00 +0100
[PATCH 08/11] ARM: DTS: am57xx-beagle-x15: Enable AFIFO use for McASP3 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
[PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-25 16:00 +0100
Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Paul Walmsley <paul@pwsan.com> - 2016-03-01 10:20 +0100
Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-03-01 17:50 +0100
Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Paul Walmsley <paul@pwsan.com> - 2016-03-01 18:10 +0100
Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-03-03 12:20 +0100
Re: [PATCH 10/11] ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8 Paul Walmsley <paul@pwsan.com> - 2016-03-03 16:40 +0100
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