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Groups > linux.kernel > #1277143
| From | Marc Zyngier <marc.zyngier@arm.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller |
| Date | 2015-11-25 11:00 +0100 |
| Message-ID | <qyF1M-4qs-5@gated-at.bofh.it> (permalink) |
| References | <qwq6R-57A-3@gated-at.bofh.it> <qypJo-2KZ-17@gated-at.bofh.it> <qyB7Q-1Td-15@gated-at.bofh.it> <qyD9D-3aA-1@gated-at.bofh.it> <qyE5I-3P7-17@gated-at.bofh.it> |
| Organization | ARM Ltd |
On Wed, 25 Nov 2015 14:23:29 +0530 Amit Tomer <amittomer25@gmail.com> wrote: > Sorry to intervene but just trying to learn from your comments. > > > You have plenty, and that's the whole of your device space. *All of it*. So > > just take the base address of your PCIe controller, and be done with > > it. > > but isn't few of PCIe controller's registers itself are mapped > here(base address). So, how can we use this address for MSI? You can, because the PCIe controller never writes to itself. If it writes to that base address, then it *is* the MSI doorbell and the bridge will hopefully do the right thing. > Or you said from base address of PCIe controller, find an offset that > can be used as MSI address? That works as well. Given the description of the HW we've been given, any address will do, as long as it is behind the PCIe RC. Thanks, M. -- Jazz is not dead. It just smells funny. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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[PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2015-11-19 06:40 +0100
Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Marc Zyngier <marc.zyngier@arm.com> - 2015-11-24 18:40 +0100
RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2015-11-25 06:50 +0100
Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Marc Zyngier <marc.zyngier@arm.com> - 2015-11-25 09:00 +0100
Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Amit Tomer <amittomer25@gmail.com> - 2015-11-25 10:00 +0100
Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Marc Zyngier <marc.zyngier@arm.com> - 2015-11-25 11:00 +0100
RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2015-11-26 06:10 +0100
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