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RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

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> On Thu, 19 Nov 2015 11:05:23 +0530
> Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> wrote:
> 
> > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> > Acked-by: Rob Herring <robh@kernel.org>
> > ---
> > +
> > +#define MSI_ADDRESS				0xDEED0000
> 
> How did you pick this value? What if it intersect with some actual RAM?
> What if a device actually does DMA to that location?
> 
> Wouldn't it make sense to actually pick a real *device* address (hint:
> your MSI controller itself) for this purpose, as the device will never DMA
> there?
>
> 
We have already mentioned in previous patch discussion, we don't have any device address on our SOC for MSI, that's 
 the reason we are allocating a page for MSI in RAM. Since our memory write is consumed by bridge and doesn't write to memory, you suggested to use 
some random address,  so using some random address.
> 
> 
> > +
> > +static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int
> virq,
> > +				unsigned int nr_irqs, void *args) {
> > +	struct nwl_pcie *pcie = domain->host_data;
> > +	struct nwl_msi *msi = &pcie->msi;
> > +	int bit;
> > +	int i;
> > +	int ret;
> > +
> > +	mutex_lock(&msi->lock);
> > +	if (nr_irqs > 1) {
> > +		ret = nwl_check_hwirq(msi, nr_irqs);
> > +		if (ret < 0) {
> > +			mutex_unlock(&msi->lock);
> > +			return ret;
> > +		}
> > +	} else {
> > +		ret = find_first_zero_bit(msi->used, INT_PCI_MSI_NR);
> > +		if (ret == INT_PCI_MSI_NR) {
> > +			mutex_unlock(&msi->lock);
> > +			return -ENOSPC;
> > +		}
> > +	}
> 
> Let's be serious for a minute. What's wrong with
> bitmap_find_next_zero_area, for example?
Ok, will explore this API and do accordingly, and address in next patch.
> 
> > +
> > +	for (i = 0; i < nr_irqs; i++) {
> > +		bit = ret + i;
> > +		set_bit(bit, msi->used);
> > +
> > +		irq_domain_set_info(domain, virq + i, bit, &nwl_irq_chip,
> > +				domain->host_data, handle_simple_irq,
> > +				NULL, NULL);
> > +	}
> > +	mutex_unlock(&msi->lock);
> > +
> > +	return 0;
> > +}
> 
> Thanks,
> 
> 	M.
> --
> Jazz is not dead. It just smells funny.
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[PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2015-11-19 06:40 +0100
  Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Marc Zyngier <marc.zyngier@arm.com> - 2015-11-24 18:40 +0100
    RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2015-11-25 06:50 +0100
      Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Marc Zyngier <marc.zyngier@arm.com> - 2015-11-25 09:00 +0100
        Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Amit Tomer <amittomer25@gmail.com> - 2015-11-25 10:00 +0100
          Re: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Marc Zyngier <marc.zyngier@arm.com> - 2015-11-25 11:00 +0100
        RE: [PATCH v9] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2015-11-26 06:10 +0100

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