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[PATCH v3 01/23] powerpc/8xx: Save r3 all the time in DTLB miss handler

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We are spending between 40 and 160 cycles with a mean of 65 cycles in
the DTLB handling routine (measured with mftbl) so make it more
simple althought it adds one instruction.
With this modification, we get three registers available at all time,
which will help with following patch.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
v2: no change
v3: no change

 arch/powerpc/kernel/head_8xx.S | 13 ++++---------
 1 file changed, 4 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 78c1eba..1557926 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -385,23 +385,20 @@ InstructionTLBMiss:
 
 	. = 0x1200
 DataStoreTLBMiss:
-#ifdef CONFIG_8xx_CPU6
 	mtspr	SPRN_SPRG_SCRATCH2, r3
-#endif
 	EXCEPTION_PROLOG_0
-	mfcr	r10
+	mfcr	r3
 
 	/* If we are faulting a kernel address, we have to use the
 	 * kernel page tables.
 	 */
-	mfspr	r11, SPRN_MD_EPN
-	IS_KERNEL(r11, r11)
+	mfspr	r10, SPRN_MD_EPN
+	IS_KERNEL(r11, r10)
 	mfspr	r11, SPRN_M_TW	/* Get level 1 table */
 	BRANCH_UNLESS_KERNEL(3f)
 	lis	r11, (swapper_pg_dir-PAGE_OFFSET)@ha
 3:
-	mtcr	r10
-	mfspr	r10, SPRN_MD_EPN
+	mtcr	r3
 
 	/* Insert level 1 index */
 	rlwimi	r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
@@ -453,9 +450,7 @@ DataStoreTLBMiss:
 	MTSPR_CPU6(SPRN_MD_RPN, r10, r3)	/* Update TLB entry */
 
 	/* Restore registers */
-#ifdef CONFIG_8xx_CPU6
 	mfspr	r3, SPRN_SPRG_SCRATCH2
-#endif
 	mtspr	SPRN_DAR, r11	/* Tag DAR */
 	EXCEPTION_EPILOG_0
 	rfi
-- 
2.1.0

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[PATCH v3 00/23] powerpc/8xx: Use large pages for RAM and IMMR and other improvments Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 12/23] powerpc32: remove ioremap_base Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 18/23] powerpc: add inline functions for cache related  instructions Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 09/23] powerpc/8xx: CONFIG_PIN_TLB unneeded for  CONFIG_PPC_EARLY_DEBUG_CPM Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 07/23] powerpc/8xx: Fix vaddr for IMMR early remap Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
    Re: [PATCH v3 07/23] powerpc/8xx: Fix vaddr for IMMR early remap kbuild test robot <lkp@intel.com> - 2015-11-17 16:50 +0100
    Re: [PATCH v3 07/23] powerpc/8xx: Fix vaddr for IMMR early remap kbuild test robot <lkp@intel.com> - 2015-11-17 17:50 +0100
  [PATCH v3 03/23] powerpc: Update documentation for noltlbs kernel parameter Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 08/23] powerpc/8xx: Map IMMR area with 512k page at a fixed  address Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 17/23] powerpc/8xx: rewrite flush_instruction_cache() in C Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 19/23] powerpc32: Remove clear_pages() and define  clear_page() inline Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 13/23] powerpc/8xx: Add missing SPRN defines into reg_8xx.h Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 20/23] powerpc32: move xxxxx_dcache_range() functions  inline Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 21/23] powerpc: Simplify test in __dma_sync() Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 01/23] powerpc/8xx: Save r3 all the time in DTLB miss handler Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 15/23] powerpc/8xx: remove special handling of CPU6 errata  in set_dec() Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 06/23] powerpc32: refactor x_mapped_by_bats() and x_mapped_by_tlbcam() together Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 10/23] powerpc/8xx: map more RAM at startup when needed Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100

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