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[PATCH v3 19/23] powerpc32: Remove clear_pages() and define clear_page() inline

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clear_pages() is never used expect by clear_page, and PPC32 is the
only architecture (still) having this function. Neither PPC64 nor
any other architecture has it.

This patch removes clear_pages() and moves clear_page() function
inline (same as PPC64) as it only is a few isns

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
v2: no change
v3: no change

 arch/powerpc/include/asm/page_32.h | 17 ++++++++++++++---
 arch/powerpc/kernel/misc_32.S      | 16 ----------------
 arch/powerpc/kernel/ppc_ksyms_32.c |  1 -
 3 files changed, 14 insertions(+), 20 deletions(-)

diff --git a/arch/powerpc/include/asm/page_32.h b/arch/powerpc/include/asm/page_32.h
index 68d73b2..6a8e179 100644
--- a/arch/powerpc/include/asm/page_32.h
+++ b/arch/powerpc/include/asm/page_32.h
@@ -1,6 +1,8 @@
 #ifndef _ASM_POWERPC_PAGE_32_H
 #define _ASM_POWERPC_PAGE_32_H
 
+#include <asm/cache.h>
+
 #if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
 #if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
 #error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
@@ -36,9 +38,18 @@ typedef unsigned long long pte_basic_t;
 typedef unsigned long pte_basic_t;
 #endif
 
-struct page;
-extern void clear_pages(void *page, int order);
-static inline void clear_page(void *page) { clear_pages(page, 0); }
+/*
+ * Clear page using the dcbz instruction, which doesn't cause any
+ * memory traffic (except to write out any cache lines which get
+ * displaced).  This only works on cacheable memory.
+ */
+static inline void clear_page(void *addr)
+{
+	unsigned int i;
+
+	for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
+		dcbz(addr);
+}
 extern void copy_page(void *to, void *from);
 
 #include <asm-generic/getorder.h>
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 72fd7a7..ce3ca08 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -517,22 +517,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
 #endif /* CONFIG_BOOKE */
 
 /*
- * Clear pages using the dcbz instruction, which doesn't cause any
- * memory traffic (except to write out any cache lines which get
- * displaced).  This only works on cacheable memory.
- *
- * void clear_pages(void *page, int order) ;
- */
-_GLOBAL(clear_pages)
-	li	r0,PAGE_SIZE/L1_CACHE_BYTES
-	slw	r0,r0,r4
-	mtctr	r0
-1:	dcbz	0,r3
-	addi	r3,r3,L1_CACHE_BYTES
-	bdnz	1b
-	blr
-
-/*
  * Copy a whole page.  We use the dcbz instruction on the destination
  * to reduce memory traffic (it eliminates the unnecessary reads of
  * the destination into cache).  This requires that the destination
diff --git a/arch/powerpc/kernel/ppc_ksyms_32.c b/arch/powerpc/kernel/ppc_ksyms_32.c
index 30ddd8a..2bfaafe 100644
--- a/arch/powerpc/kernel/ppc_ksyms_32.c
+++ b/arch/powerpc/kernel/ppc_ksyms_32.c
@@ -10,7 +10,6 @@
 #include <asm/pgtable.h>
 #include <asm/dcr.h>
 
-EXPORT_SYMBOL(clear_pages);
 EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
 EXPORT_SYMBOL(DMA_MODE_READ);
 EXPORT_SYMBOL(DMA_MODE_WRITE);
-- 
2.1.0

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[PATCH v3 00/23] powerpc/8xx: Use large pages for RAM and IMMR and other improvments Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 12/23] powerpc32: remove ioremap_base Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 18/23] powerpc: add inline functions for cache related  instructions Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 09/23] powerpc/8xx: CONFIG_PIN_TLB unneeded for  CONFIG_PPC_EARLY_DEBUG_CPM Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 07/23] powerpc/8xx: Fix vaddr for IMMR early remap Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
    Re: [PATCH v3 07/23] powerpc/8xx: Fix vaddr for IMMR early remap kbuild test robot <lkp@intel.com> - 2015-11-17 16:50 +0100
    Re: [PATCH v3 07/23] powerpc/8xx: Fix vaddr for IMMR early remap kbuild test robot <lkp@intel.com> - 2015-11-17 17:50 +0100
  [PATCH v3 03/23] powerpc: Update documentation for noltlbs kernel parameter Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 08/23] powerpc/8xx: Map IMMR area with 512k page at a fixed  address Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 17/23] powerpc/8xx: rewrite flush_instruction_cache() in C Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:10 +0100
  [PATCH v3 19/23] powerpc32: Remove clear_pages() and define  clear_page() inline Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 13/23] powerpc/8xx: Add missing SPRN defines into reg_8xx.h Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 20/23] powerpc32: move xxxxx_dcache_range() functions  inline Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 21/23] powerpc: Simplify test in __dma_sync() Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 01/23] powerpc/8xx: Save r3 all the time in DTLB miss handler Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 15/23] powerpc/8xx: remove special handling of CPU6 errata  in set_dec() Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 06/23] powerpc32: refactor x_mapped_by_bats() and x_mapped_by_tlbcam() together Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100
  [PATCH v3 10/23] powerpc/8xx: map more RAM at startup when needed Christophe Leroy <christophe.leroy@c-s.fr> - 2015-11-17 15:20 +0100

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