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Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc

From Maxime Ripard <maxime.ripard@free-electrons.com>
Newsgroups linux.kernel
Subject Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc
Date 2016-01-22 21:40 +0100
Message-ID <qTQEW-IC-7@gated-at.bofh.it> (permalink)
References <qTg8v-Im-9@gated-at.bofh.it> <qTg8D-Im-53@gated-at.bofh.it>
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Hi, 

On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
> mmc2 and mmc3 are available on the same pins, with different mux values.
> However, only mmc3 supports 8 bit DDR transfer modes.
> 
> Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
> set the drive strength to 40mA, which is needed for DDR.
> 
> This pinmux setting also includes the hardware reset pin for emmc.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> index b6ad7850fac6..1867af24ff52 100644
> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> @@ -709,6 +709,16 @@
>  				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>  			};
>  
> +			mmc3_8bit_emmc_pins: mmc3@1 {
> +				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
> +						 "PC10", "PC11", "PC12",
> +						 "PC13", "PC14", "PC15",
> +						 "PC24";
> +				allwinner,function = "mmc3";
> +				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +

Is that reset pin optional?

If so, I'd prefer it to be a separate node, like we're doing for the
SPI chip selects for example.

It allows more reusability between different devices without declaring
new nodes.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
  [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    Re: [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware  reset and HS-DDR for eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
  [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Hans de Goede <hdegoede@redhat.com> - 2016-01-21 12:20 +0100
      Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 13:30 +0100
        Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Hans de Goede <hdegoede@redhat.com> - 2016-01-21 13:30 +0100
          Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 13:30 +0100
            Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Hans de Goede <hdegoede@redhat.com> - 2016-01-21 13:40 +0100
    Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:40 +0100
      Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-23 05:30 +0100
        Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
  [PATCH RFC 02/15] mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
  [PATCH RFC 06/15] mmc: sunxi: Support 8 bit eMMC DDR transfer modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
  [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    Re: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc  compatible Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:50 +0100
      Re: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible Chen-Yu Tsai <wens@csie.org> - 2016-01-23 12:00 +0100
  [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    Re: [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset  and HS-DDR for eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:50 +0100
  [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    Re: [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in  mmc2_8bit_pins Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
  [PATCH RFC 01/15] mmc: sunxi: Document host init sequence Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
  [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    Re: [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in  mmc2_8bit_pins Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
  [PATCH RFC 07/15] mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
  [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Hans de Goede <hdegoede@redhat.com> - 2016-01-21 12:20 +0100
      Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 13:00 +0100
        Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Hans de Goede <hdegoede@redhat.com> - 2016-01-21 13:30 +0100
  [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:40 +0100
      Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Chen-Yu Tsai <wens@csie.org> - 2016-01-23 12:10 +0100
        Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
  [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    Re: [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware  reset and HS-DDR for eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
  Re: [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC  DDR modes Hans de Goede <hdegoede@redhat.com> - 2016-01-21 12:20 +0100

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