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[PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes

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  [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware  reset and HS-DDR for eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Hans de Goede <hdegoede@redhat.com> - 2016-01-21 12:20 +0100
        Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 13:30 +0100
          Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Hans de Goede <hdegoede@redhat.com> - 2016-01-21 13:30 +0100
            Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 13:30 +0100
              Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Hans de Goede <hdegoede@redhat.com> - 2016-01-21 13:40 +0100
      Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:40 +0100
        Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-23 05:30 +0100
          Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for  onboard eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    [PATCH RFC 02/15] mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    [PATCH RFC 06/15] mmc: sunxi: Support 8 bit eMMC DDR transfer modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc  compatible Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:50 +0100
        Re: [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible Chen-Yu Tsai <wens@csie.org> - 2016-01-23 12:00 +0100
    [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset  and HS-DDR for eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:50 +0100
    [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in  mmc2_8bit_pins Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    [PATCH RFC 01/15] mmc: sunxi: Document host init sequence Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in  mmc2_8bit_pins Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    [PATCH RFC 07/15] mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
    [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Hans de Goede <hdegoede@redhat.com> - 2016-01-21 12:20 +0100
        Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Chen-Yu Tsai <wens@csie.org> - 2016-01-21 13:00 +0100
          Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes Hans de Goede <hdegoede@redhat.com> - 2016-01-21 13:30 +0100
    [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-22 21:40 +0100
        Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Chen-Yu Tsai <wens@csie.org> - 2016-01-23 12:10 +0100
          Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC Chen-Yu Tsai <wens@csie.org> - 2016-01-21 06:40 +0100
      Re: [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware  reset and HS-DDR for eMMC Maxime Ripard <maxime.ripard@free-electrons.com> - 2016-01-24 18:00 +0100
    Re: [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC  DDR modes Hans de Goede <hdegoede@redhat.com> - 2016-01-21 12:20 +0100

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#1315933 — Re: [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins

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On Thu, Jan 21, 2016 at 01:26:37PM +0800, Chen-Yu Tsai wrote:
> mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
> The MMC controller also has a reset output that is supported.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1313916 — [PATCH RFC 01/15] mmc: sunxi: Document host init sequence

sunxi_mmc_init_host() originated from Allwinner kernel sources. The
magic numbers written to various registers was never documented.

Add comments for values found in Allwinner user manuals.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 83de82bceafc..cce5ca540857 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -284,16 +284,28 @@ static int sunxi_mmc_init_host(struct mmc_host *mmc)
 	if (sunxi_mmc_reset_host(host))
 		return -EIO;
 
+	/*
+	 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
+	 *
+	 * TODO: sun9i has a larger FIFO and supports higher trigger values
+	 */
 	mmc_writel(host, REG_FTRGL, 0x20070008);
+	/* Maximum timeout value */
 	mmc_writel(host, REG_TMOUT, 0xffffffff);
+	/* Unmask SDIO interrupt if needed */
 	mmc_writel(host, REG_IMASK, host->sdio_imask);
+	/* Clear all pending interrupts */
 	mmc_writel(host, REG_RINTR, 0xffffffff);
+	/* Debug register? undocumented */
 	mmc_writel(host, REG_DBGC, 0xdeb);
+	/* Enable CEATA support */
 	mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
+	/* Set DMA descriptor list base address */
 	mmc_writel(host, REG_DLBA, host->sg_dma);
 
 	rval = mmc_readl(host, REG_GCTRL);
 	rval |= SDXC_INTERRUPT_ENABLE_BIT;
+	/* Undocumented, but found in Allwinner code */
 	rval &= ~SDXC_ACCESS_DONE_DIRECT;
 	mmc_writel(host, REG_GCTRL, rval);
 
-- 
2.7.0.rc3

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#1313918 — [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins

mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
The MMC controller also has a reset output that is supported.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index f4f61b02be1a..f68b3242b33a 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -704,7 +704,8 @@
 			mmc2_8bit_pins: mmc2_8bit {
 				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
 						 "PC10", "PC11", "PC12",
-						 "PC13", "PC14", "PC15";
+						 "PC13", "PC14", "PC15",
+						 "PC16";
 				allwinner,function = "mmc2";
 				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-- 
2.7.0.rc3

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#1315934 — Re: [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins

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On Thu, Jan 21, 2016 at 01:26:40PM +0800, Chen-Yu Tsai wrote:
> mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
> The MMC controller also has a reset output that is supported.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1313919 — [PATCH RFC 07/15] mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support

Now that clock delay settings for 8 bit DDR are correct, and vqmmc
support is available, we can enable MMC_CAP_1_8V_DDR support. This
enables MMC HS-DDR at up to 52 MHz, even if signal voltage switching
is not available.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index d05928091b34..f3a7f36e38c2 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1145,6 +1145,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
 	mmc->f_min		=   400000;
 	mmc->f_max		= 50000000;
 	mmc->caps	       |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+				  MMC_CAP_1_8V_DDR |
 				  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
 
 	ret = mmc_of_parse(mmc);
-- 
2.7.0.rc3

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#1313921 — [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes

DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
Consider MMC_DDR52 when setting clock delays.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 4bec87458317..b403a2433eec 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -687,7 +687,8 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
 		oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
 		sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
 	} else if (rate <= 50000000) {
-		if (ios->timing == MMC_TIMING_UHS_DDR50) {
+		if (ios->timing == MMC_TIMING_UHS_DDR50 ||
+		    ios->timing == MMC_TIMING_MMC_DDR52) {
 			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
 			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
 		} else {
@@ -762,7 +763,8 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 	/* set ddr mode */
 	rval = mmc_readl(host, REG_GCTRL);
-	if (ios->timing == MMC_TIMING_UHS_DDR50)
+	if (ios->timing == MMC_TIMING_UHS_DDR50 ||
+	    ios->timing == MMC_TIMING_MMC_DDR52)
 		rval |= SDXC_DDR_MODE;
 	else
 		rval &= ~SDXC_DDR_MODE;
-- 
2.7.0.rc3

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#1314114 — Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes

Hi,

On 21-01-16 06:26, Chen-Yu Tsai wrote:
> DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
> Consider MMC_DDR52 when setting clock delays.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>   drivers/mmc/host/sunxi-mmc.c | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 4bec87458317..b403a2433eec 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -687,7 +687,8 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
>   		oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
>   		sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
>   	} else if (rate <= 50000000) {

Shouldn't this be <= 52000000 then, considering that we may at one point get
some PLL setup where we may actually be able to do 52000000 for MMC_TIMING_MMC_DDR52 ?

> -		if (ios->timing == MMC_TIMING_UHS_DDR50) {
> +		if (ios->timing == MMC_TIMING_UHS_DDR50 ||
> +		    ios->timing == MMC_TIMING_MMC_DDR52) {
>   			oclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].output;
>   			sclk_dly = host->clk_delays[SDXC_CLK_50M_DDR].sample;
>   		} else {
> @@ -762,7 +763,8 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>
>   	/* set ddr mode */
>   	rval = mmc_readl(host, REG_GCTRL);
> -	if (ios->timing == MMC_TIMING_UHS_DDR50)
> +	if (ios->timing == MMC_TIMING_UHS_DDR50 ||
> +	    ios->timing == MMC_TIMING_MMC_DDR52)
>   		rval |= SDXC_DDR_MODE;
>   	else
>   		rval &= ~SDXC_DDR_MODE;
>

Regards,

Hans

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#1314135 — Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes

On Thu, Jan 21, 2016 at 7:14 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>
>> DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
>> Consider MMC_DDR52 when setting clock delays.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>   drivers/mmc/host/sunxi-mmc.c | 6 ++++--
>>   1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>> index 4bec87458317..b403a2433eec 100644
>> --- a/drivers/mmc/host/sunxi-mmc.c
>> +++ b/drivers/mmc/host/sunxi-mmc.c
>> @@ -687,7 +687,8 @@ static int sunxi_mmc_clk_set_rate(struct
>> sunxi_mmc_host *host,
>>                 oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
>>                 sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
>>         } else if (rate <= 50000000) {
>
>
> Shouldn't this be <= 52000000 then, considering that we may at one point get
> some PLL setup where we may actually be able to do 52000000 for
> MMC_TIMING_MMC_DDR52 ?

Given that mmc->f_max = 50000000, the core will never try any clock rate higher
than 50 MHz, and iirc clk_round_rate always rounds down. We could increase both
numbers at the same time when we actually encounter such hardware.

Or we could increase both now, which I actually did in an earlier version, but
it really made no difference with current hardware.


Regards
ChenYu

>
>> -               if (ios->timing == MMC_TIMING_UHS_DDR50) {
>> +               if (ios->timing == MMC_TIMING_UHS_DDR50 ||
>> +                   ios->timing == MMC_TIMING_MMC_DDR52) {
>>                         oclk_dly =
>> host->clk_delays[SDXC_CLK_50M_DDR].output;
>>                         sclk_dly =
>> host->clk_delays[SDXC_CLK_50M_DDR].sample;
>>                 } else {
>> @@ -762,7 +763,8 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc,
>> struct mmc_ios *ios)
>>
>>         /* set ddr mode */
>>         rval = mmc_readl(host, REG_GCTRL);
>> -       if (ios->timing == MMC_TIMING_UHS_DDR50)
>> +       if (ios->timing == MMC_TIMING_UHS_DDR50 ||
>> +           ios->timing == MMC_TIMING_MMC_DDR52)
>>                 rval |= SDXC_DDR_MODE;
>>         else
>>                 rval &= ~SDXC_DDR_MODE;
>>
>
> Regards,
>
> Hans

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#1314153 — Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes

Hi,

On 21-01-16 12:55, Chen-Yu Tsai wrote:
> On Thu, Jan 21, 2016 at 7:14 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 21-01-16 06:26, Chen-Yu Tsai wrote:
>>>
>>> DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
>>> Consider MMC_DDR52 when setting clock delays.
>>>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>> ---
>>>    drivers/mmc/host/sunxi-mmc.c | 6 ++++--
>>>    1 file changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>>> index 4bec87458317..b403a2433eec 100644
>>> --- a/drivers/mmc/host/sunxi-mmc.c
>>> +++ b/drivers/mmc/host/sunxi-mmc.c
>>> @@ -687,7 +687,8 @@ static int sunxi_mmc_clk_set_rate(struct
>>> sunxi_mmc_host *host,
>>>                  oclk_dly = host->clk_delays[SDXC_CLK_25M].output;
>>>                  sclk_dly = host->clk_delays[SDXC_CLK_25M].sample;
>>>          } else if (rate <= 50000000) {
>>
>>
>> Shouldn't this be <= 52000000 then, considering that we may at one point get
>> some PLL setup where we may actually be able to do 52000000 for
>> MMC_TIMING_MMC_DDR52 ?
>
> Given that mmc->f_max = 50000000, the core will never try any clock rate higher
> than 50 MHz, and iirc clk_round_rate always rounds down. We could increase both
> numbers at the same time when we actually encounter such hardware.

I'm afraid that someone may increase mmc->f_max = 50000000 at one point without
adjusting the rate checks above at the same time, so lets update both of them now.

Regards,

Hans

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#1313922 — [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc

mmc2 and mmc3 are available on the same pins, with different mux values.
However, only mmc3 supports 8 bit DDR transfer modes.

Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
set the drive strength to 40mA, which is needed for DDR.

This pinmux setting also includes the hardware reset pin for emmc.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index b6ad7850fac6..1867af24ff52 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -709,6 +709,16 @@
 				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 			};
 
+			mmc3_8bit_emmc_pins: mmc3@1 {
+				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
+						 "PC10", "PC11", "PC12",
+						 "PC13", "PC14", "PC15",
+						 "PC24";
+				allwinner,function = "mmc3";
+				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
 			gmac_pins_mii_a: gmac_mii@0 {
 				allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 						"PA8", "PA9", "PA11",
-- 
2.7.0.rc3

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#1315258 — Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc

[Multipart message — attachments visible in raw view] — view raw

Hi, 

On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
> mmc2 and mmc3 are available on the same pins, with different mux values.
> However, only mmc3 supports 8 bit DDR transfer modes.
> 
> Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
> set the drive strength to 40mA, which is needed for DDR.
> 
> This pinmux setting also includes the hardware reset pin for emmc.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> index b6ad7850fac6..1867af24ff52 100644
> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> @@ -709,6 +709,16 @@
>  				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>  			};
>  
> +			mmc3_8bit_emmc_pins: mmc3@1 {
> +				allwinner,pins = "PC6", "PC7", "PC8", "PC9",
> +						 "PC10", "PC11", "PC12",
> +						 "PC13", "PC14", "PC15",
> +						 "PC24";
> +				allwinner,function = "mmc3";
> +				allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +

Is that reset pin optional?

If so, I'd prefer it to be a separate node, like we're doing for the
SPI chip selects for example.

It allows more reusability between different devices without declaring
new nodes.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1315577 — Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc

Hi,

On Sat, Jan 23, 2016 at 4:31 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
>> mmc2 and mmc3 are available on the same pins, with different mux values.
>> However, only mmc3 supports 8 bit DDR transfer modes.
>>
>> Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
>> set the drive strength to 40mA, which is needed for DDR.
>>
>> This pinmux setting also includes the hardware reset pin for emmc.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
>> index b6ad7850fac6..1867af24ff52 100644
>> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
>> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
>> @@ -709,6 +709,16 @@
>>                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>>                       };
>>
>> +                     mmc3_8bit_emmc_pins: mmc3@1 {
>> +                             allwinner,pins = "PC6", "PC7", "PC8", "PC9",
>> +                                              "PC10", "PC11", "PC12",
>> +                                              "PC13", "PC14", "PC15",
>> +                                              "PC24";
>> +                             allwinner,function = "mmc3";
>> +                             allwinner,drive = <SUN4I_PINCTRL_40_MA>;
>> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +                     };
>> +
>
> Is that reset pin optional?
>
> If so, I'd prefer it to be a separate node, like we're doing for the
> SPI chip selects for example.
>
> It allows more reusability between different devices without declaring
> new nodes.

All eMMC devices have a reset pin. The MMC standard specifies this as
one way to reset the card, others being a special reset command, or
powering the card off. It also notes a state when the card will not
accept commands, and will require a power cycle or asserting the reset
pin.

I assume all designs would route this pin. The FEX files also have this
pin included by default.


Regards
ChenYu

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#1315931 — Re: [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc

[Multipart message — attachments visible in raw view] — view raw

Hi,

On Sat, Jan 23, 2016 at 07:04:54PM +0800, Chen-Yu Tsai wrote:
> Hi,
> 
> On Sat, Jan 23, 2016 at 4:31 AM, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > Hi,
> >
> > On Thu, Jan 21, 2016 at 01:26:35PM +0800, Chen-Yu Tsai wrote:
> >> mmc2 and mmc3 are available on the same pins, with different mux values.
> >> However, only mmc3 supports 8 bit DDR transfer modes.
> >>
> >> Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
> >> set the drive strength to 40mA, which is needed for DDR.
> >>
> >> This pinmux setting also includes the hardware reset pin for emmc.
> >>
> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> ---
> >>  arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++
> >>  1 file changed, 10 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
> >> index b6ad7850fac6..1867af24ff52 100644
> >> --- a/arch/arm/boot/dts/sun6i-a31.dtsi
> >> +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
> >> @@ -709,6 +709,16 @@
> >>                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >>                       };
> >>
> >> +                     mmc3_8bit_emmc_pins: mmc3@1 {
> >> +                             allwinner,pins = "PC6", "PC7", "PC8", "PC9",
> >> +                                              "PC10", "PC11", "PC12",
> >> +                                              "PC13", "PC14", "PC15",
> >> +                                              "PC24";
> >> +                             allwinner,function = "mmc3";
> >> +                             allwinner,drive = <SUN4I_PINCTRL_40_MA>;
> >> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> >> +                     };
> >> +
> >
> > Is that reset pin optional?
> >
> > If so, I'd prefer it to be a separate node, like we're doing for the
> > SPI chip selects for example.
> >
> > It allows more reusability between different devices without declaring
> > new nodes.
> 
> All eMMC devices have a reset pin. The MMC standard specifies this as
> one way to reset the card, others being a special reset command, or
> powering the card off. It also notes a state when the card will not
> accept commands, and will require a power cycle or asserting the reset
> pin.
> 
> I assume all designs would route this pin. The FEX files also have this
> pin included by default.

I was more concerned about the case were you'd have a 8bits bus
without an emmc. But I guess that can't happen, since all SD cards are
using a 4 bits width anyway.

I'll apply this patch.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1313923 — [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC

mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.

Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index c0060e4f7379..958160e40fd0 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -174,9 +174,15 @@
 	vmmc-supply = <&reg_vcc3v0>;
 	bus-width = <8>;
 	non-removable;
+	cap-mmc-hw-reset;
 	status = "okay";
 };
 
+&mmc2_8bit_pins {
+	/* Increase drive strength for DDR modes */
+	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
 &reg_usb1_vbus {
 	pinctrl-0 = <&usb1_vbus_pin_optimus>;
 	gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-- 
2.7.0.rc3

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#1315927 — Re: [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC

[Multipart message — attachments visible in raw view] — view raw

On Thu, Jan 21, 2016 at 01:26:41PM +0800, Chen-Yu Tsai wrote:
> mmc2 has a special pin for eMMC hardware reset, which is controllable
> from the controller. Add the "mmc-cap-hw-reset" property to denote that
> this controller supports this function, and the pins are actually used.
> 
> Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
> support.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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#1314113 — Re: [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes

Hi,

On 21-01-16 06:26, Chen-Yu Tsai wrote:
> Hi everyone,
>
> This series adds support for vqmmc regulator and eMMC DDR modes for
> sunxi-mmc. Allwinner's MMC controller supports eMMC 4.41 on earlier
> SoCs, and up to 5.0 on latest ones. UHS-1 modes are also supported
> by the hardware, but these are not covered in this series, as no
> boards have dedicated regulators for vqmmc.
>
> To support these faster modes, these patches adds vqmmc regulator
> support, which is used by the mmc core to switch to faster modes,
> even if the signaling voltage is fixed. Signal voltage switching
> support is also added, but not tested, as no available hardware has
> a dedicated vqmmc regulator.
>
> Support for eMMC reset in the controller, vs a GPIO and pwrseq, is
> also added where applicable.

Thanks for working on this. I've send my remarks to a few of the patches,
the ones I've not remarked on look good to me.

Regards,

Hans


>
> Patch 1 documents the mmc host init sequence. When the driver was
> ported, this part was copied verbatim and not documented. With inline
> comments from later SDKs and datasheet register definitions, this part
> is now clearer.
>
> Patch 2 makes the .set_ios callback return on errors from
> mmc_regulator_set_ocr.
>
> Patch 3 adds support (enabling/disable, and voltage control) for vqmmc
> regulator to sunxi-mmc.
>
> Patch 4 adds support signal voltage switch for the mmc controller. The
> Allwinner MMC controller uses a special bit for sending signal voltage
> switching command.
>
> Patch 5 adds timing delays for MMC_DDR52 mode.
>
> Patch 6 adds support for 8 bit eMMC DDR52 mode. Under this mode, the
> controller must run at twice the card clock, and different timing delays
> are needed.
>
> Patch 7 enables eMMC HS-DDR for sunxi-mmc.
>
> Patch 8 adds mmc3 pins for 8 bit emmc for A31/A31s.
>
> Patch 9 switches from mmc2 to mmc3 for the onboard eMMC on Sinlinx
> SinA31s. According to Allwinner, only mmc3 supports eMMC DDR52 on
> A31/A31s.
>
> Patch 10 adds the eMMC reset pin to the emmc pingroup for A23/A33.
>
> Patch 11 enables eMMC hardware reset and eMMC DDR52 mode for SinA33.
>
> Patch 12 switches A80 to sun9i specific mmc compatible. A80 has different
> timing delays, and a larger FIFO (TODO).
>
> Patch 13 adds the eMMC reset pin to the emmc pingroup for A80.
>
> Patch 14 enables eMMC hardware reset and eMMC DDR52 mode for A80 Optimus.
>
> Patch 15 enables eMMC hardware reset and eMMC DDR52 mode for Cubieboard4.
>
> Chen-Yu Tsai (15):
>    mmc: sunxi: Document host init sequence
>    mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios
>      op
>    mmc: sunxi: Block signal voltage switching (CMD11)
>    mmc: sunxi: Support vqmmc regulator
>    mmc: sunxi: Support MMC_DDR52 timing modes
>    mmc: sunxi: Support 8 bit eMMC DDR transfer modes
>    mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support
>    ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc
>    ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC
>    ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins
>    ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC
>    ARM: dts: sun9i: Use sun9i specific mmc compatible
>    ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins
>    ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for
>      eMMC
>    ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for
>      eMMC
>
>   arch/arm/boot/dts/sun6i-a31.dtsi               | 10 +++
>   arch/arm/boot/dts/sun6i-a31s-sina31s-core.dtsi |  6 +-
>   arch/arm/boot/dts/sun8i-a23-a33.dtsi           |  2 +-
>   arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts |  3 +
>   arch/arm/boot/dts/sun9i-a80-cubieboard4.dts    |  6 ++
>   arch/arm/boot/dts/sun9i-a80-optimus.dts        |  6 ++
>   arch/arm/boot/dts/sun9i-a80.dtsi               | 11 +--
>   drivers/mmc/host/sunxi-mmc.c                   | 98 +++++++++++++++++++++++---
>   8 files changed, 126 insertions(+), 16 deletions(-)
>

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