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Groups > linux.kernel > #1281733

[PATCH v3 19/19] irqchip/mips-gic: Add new DT property to reserve IPIs

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The new property will allow to specify the range of GIC hwirqs to use for IPIs.

This is an optinal property. We preserve the previous behaviour of allocating
the last 2 * gic_vpes if it's not specified or DT is not supported.

Signed-off-by: Qais Yousef <qais.yousef@imgtec.com>
Acked-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/interrupt-controller/mips-gic.txt    |  7 +++++++
 drivers/irqchip/irq-mips-gic.c                               | 12 ++++++++++--
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
index aae4c384ee1f..173595305e26 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mips-gic.txt
@@ -23,6 +23,12 @@ Optional properties:
 - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
   to which the GIC may not route interrupts.  Valid values are 2 - 7.
   This property is ignored if the CPU is started in EIC mode.
+- mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
+  reserved for IPIs.
+  It accepts 2 values, the 1st is the starting interrupt and the 2nd is the size
+  of the reserved range.
+  If not specified, the driver will allocate the last 2 * number of VPEs in the
+  system.
 
 Required properties for timer sub-node:
 - compatible : Should be "mti,gic-timer".
@@ -44,6 +50,7 @@ Example:
 		#interrupt-cells = <3>;
 
 		mti,reserved-cpu-vectors = <7>;
+		mti,reserved-ipi-vectors = <40 8>;
 
 		timer {
 			compatible = "mti,gic-timer";
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 77200da9d8d3..055aa513295c 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -944,6 +944,7 @@ static void __init __gic_init(unsigned long gic_base_addr,
 			      struct device_node *node)
 {
 	unsigned int gicconfig;
+	unsigned int v[2];
 
 	gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
 
@@ -1012,8 +1013,15 @@ static void __init __gic_init(unsigned long gic_base_addr,
 
 	gic_ipi_domain->bus_token = DOMAIN_BUS_IPI;
 
-	/* Make the last 2 * NR_CPUS available for IPIs */
-	bitmap_set(ipi_resrv, gic_shared_intrs - 2 * gic_vpes, 2 * gic_vpes);
+	if (node &&
+	    !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
+		bitmap_set(ipi_resrv, v[0], v[1]);
+	} else {
+		/* Make the last 2 * gic_vpes available for IPIs */
+		bitmap_set(ipi_resrv,
+			   gic_shared_intrs - 2 * gic_vpes,
+			   2 * gic_vpes);
+	}
 
 	gic_basic_init();
 }
-- 
2.1.0

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Thread

[PATCH v3 00/19] Implement generic IPI support mechanism Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 01/19] genirq: Add new IRQ_DOMAIN_FLAGS_IPI Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 04/19] genirq: Add struct ipi_mapping and its helper functions Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 08/19] genirq: Add a new generic IPI reservation code to irq core Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 11/19] genirq: Implement ipi_send_{mask, single}() Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 09/19] genirq: Add a new function to get IPI reverse mapping Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 17/19] MIPS: Make smp CMP, CPS and MT use the new generic IPI functions Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 18/19] MIPS: Delete smp-gic.c Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 03/19] genirq: Add GENERIC_IRQ_IPI Kconfig symbol Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 02/19] genirq: Add DOMAIN_BUS_IPI Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 05/19] genirq: Add ipi_offset to irq_common_data Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 13/19] irqchip/mips-gic: Add device hierarchy domain Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 19/19] irqchip/mips-gic: Add new DT property to reserve IPIs Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 07/19] genirq: Make irq_domain_alloc_descs() non static Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 10/19] genirq: Add a new irq_send_ipi() to irq_chip Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 16/19] MIPS: Add generic SMP IPI support Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 06/19] genirq: Add an extra comment about the use of affinity in irq_common_data Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100
  [PATCH v3 12/19] irqchip/mips-gic: Add a IPI hierarchy domain Qais Yousef <qais.yousef@imgtec.com> - 2015-12-02 13:30 +0100

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