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[PATCH 10/15] x86, fpu: rework MPX 'xstate' types

From Dave Hansen <dave@sr71.net>
Newsgroups linux.kernel
Subject [PATCH 10/15] x86, fpu: rework MPX 'xstate' types
Date 2015-09-01 00:30 +0200
Message-ID <q3FKr-4gF-29@gated-at.bofh.it> (permalink)
References <q3FKq-4gF-3@gated-at.bofh.it>
Organization linux.* mail to news gateway

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From: Dave Hansen <dave.hansen@linux.intel.com>

MPX includes two separate "extended state components".  There is
no real need to have an 'mpx_struct' because we never really
manage the states together.

We also separate out the actual data in 'mpx_bndcsr_state' from
the padding.  We will shortly be checking the state sizes against
our structures and need them to match.  For consistency, we also
ensure to prefix these types with 'mpx_'.

Lastly, we add some comments to mirror some of the descriptions
in the Intel documents (SDM) of the various state components.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: x86@kernel.org
Cc: Borislav Petkov <bp@alien8.de>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: Tim Chen <tim.c.chen@linux.intel.com>
Cc: linux-kernel@vger.kernel.org
---

 b/arch/x86/include/asm/fpu/types.h |   33 +++++++++++++++++++++++++--------
 b/arch/x86/include/asm/trace/mpx.h |    7 ++++---
 b/arch/x86/kernel/traps.c          |    2 +-
 b/arch/x86/mm/mpx.c                |    9 +++++----
 4 files changed, 35 insertions(+), 16 deletions(-)

diff -puN arch/x86/include/asm/fpu/types.h~x86-fpu-rework-mpx-types arch/x86/include/asm/fpu/types.h
--- a/arch/x86/include/asm/fpu/types.h~x86-fpu-rework-mpx-types	2015-08-31 15:17:35.427929527 -0700
+++ b/arch/x86/include/asm/fpu/types.h	2015-08-31 15:17:35.436929938 -0700
@@ -141,20 +141,37 @@ struct ymmh_struct {
 };
 
 /* Intel MPX support: */
-struct bndreg {
+
+struct mpx_bndreg {
 	u64				lower_bound;
 	u64				upper_bound;
 } __packed;
+/*
+ * State component 3 is used for the 4 128-bit bounds registers
+ */
+struct mpx_bndreg_state {
+	struct mpx_bndreg		bndreg[4];
+} __packed;
 
-struct bndcsr {
-	u64				bndcfgu;
-	u64				bndstatus;
+/*
+ * State component 4 is used for the 64-bit user-mode MPX
+ * configuration register BNDCFGU and the 64-bit MPX status
+ * register BNDSTATUS.  We call the pair "BNDCSR".
+ */
+struct mpx_bndcsr {
+ 	u64				bndcfgu;
+ 	u64				bndstatus;
 } __packed;
 
-struct mpx_struct {
-	struct bndreg			bndreg[4];
-	struct bndcsr			bndcsr;
-};
+/*
+ * The BNDCSR state is padded out to be 64-bytes in size.
+ */
+struct mpx_bndcsr_state {
+	union {
+		struct mpx_bndcsr		bndcsr;
+		u8				pad_to_64_bytes[64];
+	};
+} __packed;
 
 struct xstate_header {
 	u64				xfeatures;
diff -puN arch/x86/include/asm/trace/mpx.h~x86-fpu-rework-mpx-types arch/x86/include/asm/trace/mpx.h
--- a/arch/x86/include/asm/trace/mpx.h~x86-fpu-rework-mpx-types	2015-08-31 15:17:35.429929618 -0700
+++ b/arch/x86/include/asm/trace/mpx.h	2015-08-31 15:17:35.436929938 -0700
@@ -11,7 +11,7 @@
 TRACE_EVENT(mpx_bounds_register_exception,
 
 	TP_PROTO(void *addr_referenced,
-		 const struct bndreg *bndreg),
+		 const struct mpx_bndreg *bndreg),
 	TP_ARGS(addr_referenced, bndreg),
 
 	TP_STRUCT__entry(
@@ -44,7 +44,7 @@ TRACE_EVENT(mpx_bounds_register_exceptio
 
 TRACE_EVENT(bounds_exception_mpx,
 
-	TP_PROTO(const struct bndcsr *bndcsr),
+	TP_PROTO(const struct mpx_bndcsr *bndcsr),
 	TP_ARGS(bndcsr),
 
 	TP_STRUCT__entry(
@@ -116,7 +116,8 @@ TRACE_EVENT(mpx_new_bounds_table,
 /*
  * This gets used outside of MPX-specific code, so we need a stub.
  */
-static inline void trace_bounds_exception_mpx(const struct bndcsr *bndcsr)
+static inline
+void trace_bounds_exception_mpx(const struct mpx_bndcsr *bndcsr)
 {
 }
 
diff -puN arch/x86/kernel/traps.c~x86-fpu-rework-mpx-types arch/x86/kernel/traps.c
--- a/arch/x86/kernel/traps.c~x86-fpu-rework-mpx-types	2015-08-31 15:17:35.431929709 -0700
+++ b/arch/x86/kernel/traps.c	2015-08-31 15:17:35.437929984 -0700
@@ -372,7 +372,7 @@ dotraplinkage void do_double_fault(struc
 dotraplinkage void do_bounds(struct pt_regs *regs, long error_code)
 {
 	enum ctx_state prev_state;
-	const struct bndcsr *bndcsr;
+	const struct mpx_bndcsr *bndcsr;
 	siginfo_t *info;
 
 	prev_state = exception_enter();
diff -puN arch/x86/mm/mpx.c~x86-fpu-rework-mpx-types arch/x86/mm/mpx.c
--- a/arch/x86/mm/mpx.c~x86-fpu-rework-mpx-types	2015-08-31 15:17:35.432929755 -0700
+++ b/arch/x86/mm/mpx.c	2015-08-31 15:17:35.437929984 -0700
@@ -274,7 +274,8 @@ bad_opcode:
  */
 siginfo_t *mpx_generate_siginfo(struct pt_regs *regs)
 {
-	const struct bndreg *bndregs, *bndreg;
+	const struct mpx_bndreg_state *bndregs;
+	const struct mpx_bndreg *bndreg;
 	siginfo_t *info = NULL;
 	struct insn insn;
 	uint8_t bndregno;
@@ -301,7 +302,7 @@ siginfo_t *mpx_generate_siginfo(struct p
 		goto err_out;
 	}
 	/* now go select the individual register in the set of 4 */
-	bndreg = &bndregs[bndregno];
+	bndreg = &bndregs->bndreg[bndregno];
 
 	info = kzalloc(sizeof(*info), GFP_KERNEL);
 	if (!info) {
@@ -343,7 +344,7 @@ err_out:
 
 static __user void *mpx_get_bounds_dir(void)
 {
-	const struct bndcsr *bndcsr;
+	const struct mpx_bndcsr *bndcsr;
 
 	if (!cpu_feature_enabled(X86_FEATURE_MPX))
 		return MPX_INVALID_BOUNDS_DIR;
@@ -526,7 +527,7 @@ out_unmap:
 static int do_mpx_bt_fault(void)
 {
 	unsigned long bd_entry, bd_base;
-	const struct bndcsr *bndcsr;
+	const struct mpx_bndcsr *bndcsr;
 	struct mm_struct *mm = current->mm;
 
 	bndcsr = get_xsave_field_ptr(XFEATURE_MASK_BNDCSR);
_
--
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Thread

[PATCH 00/15] [v3] x86, fpu: XSAVE cleanups and sanity checks Dave Hansen <dave@sr71.net> - 2015-09-01 00:30 +0200
  [PATCH 10/15] x86, fpu: rework MPX 'xstate' types Dave Hansen <dave@sr71.net> - 2015-09-01 00:30 +0200
  [PATCH 15/15] x86, fpu: check CPU-provided sizes against struct declarations Dave Hansen <dave@sr71.net> - 2015-09-01 00:30 +0200
  [PATCH 02/15] x86, fpu: move XSAVE-disabling code to a helper Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200
  [PATCH 13/15] x86, fpu: correct and check XSAVE xstate size calculations Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200
  [PATCH 05/15] x86, fpu: XSAVE macro renames Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200
    Re: [PATCH 05/15] x86, fpu: XSAVE macro renames Dave Hansen <dave@sr71.net> - 2015-09-01 01:50 +0200
  [PATCH 11/15] x86, fpu: rework YMM definition Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200
  [PATCH 06/15] x86, fpu: rename XFEATURES_NR_MAX Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200
  [PATCH 04/15] x86, fpu: kill LWP support Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200
  [PATCH 09/15] x86, fpu: add helper xfeature_enabled() instead of test_bit() Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200
  [PATCH 07/15] x86, fpu: rework XSTATE_* macros to remove magic '2' Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200
  [PATCH 12/15] x86, fpu: add C structures for AVX-512 state components Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200
  [PATCH 03/15] x86, fpu: remove XSTATE_RESERVE Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200
  [PATCH 08/15] x86, fpu: remove xfeature_nr Dave Hansen <dave@sr71.net> - 2015-09-01 00:40 +0200

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