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Re: Verilog-Frage von VHDL-Programmierer

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On 09/22/2015 02:34 PM, Mathias Weierganz wrote:
[...]
> 
> reg [2:0] sr;
> reg i_latch;
> 
> always @(posedge i or posedge sr[1]) begin
>     if (sr[1] == 1) begin
>         i_latch <= 0;
>     end else begin
>         i_latch <= 1;
>     end
> end
> 
> always @(posedge clk) begin
>     sr[0] <= i_latch;
>     sr[2:1] <= sr[1:0];
>     oi <= sr[1] &~ sr[2];
> end
> 
> assign o = oi;
> endmodule

kommen nur X 'raus?
Kannst du das sr[] am anfang auf 0 setzen? 
(ich glaube mit einem initial block)

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Verilog-Frage von VHDL-Programmierer Mathias Weierganz <mathias.weierganz@gmx.net> - 2015-09-22 14:34 +0200
  Re: Verilog-Frage von VHDL-Programmierer Johann Klammer <klammerj@NOSPAM.a1.net> - 2015-09-22 15:37 +0200
    Re: Verilog-Frage von VHDL-Programmierer Mathias Weierganz <mathias.weierganz@gmx.net> - 2015-09-22 15:49 +0200
      Re: Verilog-Frage von VHDL-Programmierer Johann Klammer <klammerj@NOSPAM.a1.net> - 2015-09-22 21:54 +0200
        Re: Verilog-Frage von VHDL-Programmierer Mathias Weierganz <mathias.weierganz@gmx.net> - 2015-09-23 08:06 +0200
  Re: Verilog-Frage von VHDL-Programmierer Mathias Weierganz <mathias.weierganz@gmx.net> - 2015-09-23 11:41 +0200

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