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Re: questions about memory_order_seq_cst fence

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Masakuni Oishi wrote:
[...]
> 
> Now, back to my first question.
> 
> /***************/
> // Initially
> atomic<int> x(0), y(0);
> 
> // Thread 1:
> x.store(1, memory_order_relaxed);
> 
> // Thread 2:
> r1 = x.load(memory_order_relaxed);
> atomic_thread_fence(memory_order_seq_cst);
> r2 = y.load(memory_order_relaxed);
> 
> // Thread 3:
> y.store(1, memory_order_relaxed);
> atomic_thread_fence(memory_order_seq_cst);
> r3 = x.load(memory_order_relaxed);
> /***************/
> 
> In this code, is there any hardware that permits
> the outcome r1 == 1 && r2 == 0 && r3 == 0?

Itanium memory model permits the outcome r1 == 1 && r2 == 0 && r3 == 0
with plain st for relaxed stores.

> 
> If not, I want C++MM to prohibit such outcome.

The final draft C++MM prohibits such outcome nevertheless and thus
relaxed stores must use st.rel on Itanium.

regards,
alexander.

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Re: questions about memory_order_seq_cst fence Masakuni Oishi <yamasa@bsdhouse.org> - 2011-07-02 11:15 -0700
  Re: questions about memory_order_seq_cst fence Alexander Terekhov <terekhov@web.de> - 2011-07-05 10:07 +0200

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