Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > comp.programming.threads > #381 > unrolled thread

Re: questions about memory_order_seq_cst fence

Back to article view | Back to comp.programming.threads

Contents

  Re: questions about memory_order_seq_cst fence Masakuni Oishi <yamasa@bsdhouse.org> - 2011-07-02 11:15 -0700
    Re: questions about memory_order_seq_cst fence Alexander Terekhov <terekhov@web.de> - 2011-07-05 10:07 +0200

#381 — Re: questions about memory_order_seq_cst fence

Alexander Terekhov wrote:
> It turns out that Itanium doesn't respect read-after-read dependence
> (two loads from the same location without a store to the same location
> in-between in program order) for plain ld. As long as C++11 requires
> such coherence (makes sense, PowerPC does respect RAR dependence),
> ld.acq must be used instead of plain ld.
> 
> Plain st can not be used for memory_order_relaxed stores as well because
> in some cases C++11 requires remote write atomicity for
> memory_order_relaxed stores (Joshua Maurice posted here examples) and
> hence st.rel (it provides remote write atomicity) must be used instead
> of plain st. 

I see.

Now, back to my first question.

/***************/
// Initially
atomic<int> x(0), y(0);

// Thread 1:
x.store(1, memory_order_relaxed);

// Thread 2:
r1 = x.load(memory_order_relaxed);
atomic_thread_fence(memory_order_seq_cst);
r2 = y.load(memory_order_relaxed);

// Thread 3:
y.store(1, memory_order_relaxed);
atomic_thread_fence(memory_order_seq_cst);
r3 = x.load(memory_order_relaxed);
/***************/

In this code, is there any hardware that permits
the outcome r1 == 1 && r2 == 0 && r3 == 0?

If not, I want C++MM to prohibit such outcome.

-- 
masakuni

[toc] | [next] | [standalone]

#382

Masakuni Oishi wrote:
[...]
> 
> Now, back to my first question.
> 
> /***************/
> // Initially
> atomic<int> x(0), y(0);
> 
> // Thread 1:
> x.store(1, memory_order_relaxed);
> 
> // Thread 2:
> r1 = x.load(memory_order_relaxed);
> atomic_thread_fence(memory_order_seq_cst);
> r2 = y.load(memory_order_relaxed);
> 
> // Thread 3:
> y.store(1, memory_order_relaxed);
> atomic_thread_fence(memory_order_seq_cst);
> r3 = x.load(memory_order_relaxed);
> /***************/
> 
> In this code, is there any hardware that permits
> the outcome r1 == 1 && r2 == 0 && r3 == 0?

Itanium memory model permits the outcome r1 == 1 && r2 == 0 && r3 == 0
with plain st for relaxed stores.

> 
> If not, I want C++MM to prohibit such outcome.

The final draft C++MM prohibits such outcome nevertheless and thus
relaxed stores must use st.rel on Itanium.

regards,
alexander.

[toc] | [prev] | [standalone]

Back to top | Article view | comp.programming.threads

csiph-web