Path: csiph.com!x330-a1.tempe.blueboxinc.net!newsfeed.hal-mli.net!feeder3.hal-mli.net!news.glorb.com!feeder.erje.net!eternal-september.org!feeder.eternal-september.org!.POSTED!not-for-mail
From: Alexander Terekhov <terekhov@web.de>
Newsgroups: comp.programming.threads
Subject: Re: questions about memory_order_seq_cst fence
Date: Tue, 05 Jul 2011 10:07:20 +0200
Organization: A noiseless patient Spider
Lines: 38
Message-ID: <4E12C638.3CAF7BB7@web.de>
References: <ff1d36be-324f-4e60-958b-6ab924a82b87@glegroupsg2000goo.googlegroups.com>
Reply-To: terekhov@web.de
Mime-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Injection-Info: mx04.eternal-september.org; posting-host="MCbSEzW5qwGLFMNXJh39IQ"; logging-data="32148"; mail-complaints-to="abuse@eternal-september.org";	posting-account="U2FsdGVkX18uJwKHTGFWcm2uLD/dYdwlzswtmh9FD7w="
X-Mailer: Mozilla 4.77 [en] (Windows NT 5.0; U)
X-Accept-Language: en
Cancel-Lock: sha1:o6t5bEwhFWEjP/0GXRsPdhCt7u0=
Xref: x330-a1.tempe.blueboxinc.net comp.programming.threads:382


Masakuni Oishi wrote:
[...]
> 
> Now, back to my first question.
> 
> /***************/
> // Initially
> atomic<int> x(0), y(0);
> 
> // Thread 1:
> x.store(1, memory_order_relaxed);
> 
> // Thread 2:
> r1 = x.load(memory_order_relaxed);
> atomic_thread_fence(memory_order_seq_cst);
> r2 = y.load(memory_order_relaxed);
> 
> // Thread 3:
> y.store(1, memory_order_relaxed);
> atomic_thread_fence(memory_order_seq_cst);
> r3 = x.load(memory_order_relaxed);
> /***************/
> 
> In this code, is there any hardware that permits
> the outcome r1 == 1 && r2 == 0 && r3 == 0?

Itanium memory model permits the outcome r1 == 1 && r2 == 0 && r3 == 0
with plain st for relaxed stores.

> 
> If not, I want C++MM to prohibit such outcome.

The final draft C++MM prohibits such outcome nevertheless and thus
relaxed stores must use st.rel on Itanium.

regards,
alexander.