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Groups > comp.lang.forth > #49421 > unrolled thread
| Started by | rickman <gnuarm@gmail.com> |
|---|---|
| First post | 2016-07-24 22:29 -0400 |
| Last post | 2016-07-29 05:42 -0700 |
| Articles | 7 on this page of 67 — 13 participants |
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Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 22:29 -0400
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:01 -0400
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:05 -0400
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 22:25 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 00:08 -0400
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 23:57 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:22 -0400
Re: Forth in VHDL Paul Rubin <no.email@nospam.invalid> - 2016-07-24 22:38 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:53 -0400
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 05:31 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 05:36 -0700
Re: Forth in VHDL Richard Owlett <rowlett@cloud85.net> - 2016-07-25 08:14 -0500
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 07:37 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 08:01 -0700
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 14:11 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 17:39 -0400
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 18:01 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 19:40 -0400
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-26 11:04 +0100
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 11:13 -0400
Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-26 16:00 +0000
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 12:58 -0400
Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-27 09:39 +0000
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 10:01 -0400
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-27 22:46 +0100
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-26 09:43 -0700
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-28 09:12 +0100
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 05:04 -0400
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-28 07:56 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 13:04 -0400
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-08-02 12:21 +0100
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-28 08:02 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 18:15 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-28 15:19 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-31 18:43 -0400
Re: Forth in VHDL Paul Rubin <no.email@nospam.invalid> - 2016-07-31 17:10 -0700
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-24 20:08 -0700
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-24 20:33 -0700
Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 22:58 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 00:17 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-25 10:02 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 14:13 -0400
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 14:17 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-25 15:04 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 19:28 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-25 17:20 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 23:07 -0400
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-26 03:07 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 13:05 -0400
Re: Forth in VHDL Brad Eckert <hwfwguy@gmail.com> - 2016-07-26 16:22 -0700
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-27 03:57 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 10:34 -0400
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-27 11:15 -0500
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 12:51 -0400
Re: Forth in VHDL Andrew Haley <andrew29@littlepinkcloud.invalid> - 2016-07-27 16:12 -0500
Re: Forth in VHDL "Elizabeth D. Rather" <erather@forth.com> - 2016-07-27 12:43 -1000
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 00:40 -0400
Re: Forth in VHDL hughaguilar96@gmail.com - 2016-08-02 22:45 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-28 00:39 -0400
Re: Forth in VHDL wzab01@gmail.com - 2016-07-25 01:48 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 05:57 -0700
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-07-25 06:02 -0700
Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-30 16:40 +0100
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-08-01 08:58 -0700
Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-31 17:10 -0400
Re: Forth in VHDL JUERGEN <epldfpga@aol.com> - 2016-08-01 09:02 -0700
Re: Forth in VHDL Ilya Tarasov <ilya74.tarasov@gmail.com> - 2016-07-29 05:42 -0700
Page 4 of 4 — ← Prev page 1 2 3 [4]
| From | JUERGEN <epldfpga@aol.com> |
|---|---|
| Date | 2016-07-25 05:57 -0700 |
| Message-ID | <75a5e2b8-5d09-4f7d-b0b5-0ca36a019752@googlegroups.com> |
| In reply to | #49421 |
On Monday, July 25, 2016 at 3:29:28 AM UTC+1, rickman wrote: > I wonder how hard it would be to write a Forth in VHDL? It would likely > be as easy to do in non-synthesizable code as any other language. It > might be a bit harder in synthesizable code. For one, the I/O would > need to be constructed from scratch based on some hardware interface. > The non-synthesizable code could just read from a file... I wonder if > you can read from the console in VHDL? I've never tried that before. > > -- > > Rick C Forth to Gates - I had a discussion with Ian page last year - he developed C to gates in Oxford if I remember correctly. The product route: Handel-C - then ESL then Celoxica then Mentor. If you can do C to Gates - Forth to Gates should be easier? He stated it should not be too difficult and said: "I am willing to give advice, however I’ve been out of academia for 14 years now - and haven’t written a program in any language in all that time! - so I am inevitably going to be rather out of touch with practical aspects which makes me unsure where I might be able to be of real help. The starting point for the other compiler builders I mentioned was the attached 1991 paper. You basically build a global hardware graph as you parse the input program. In the Handel model, all the rhs expressions are state-free, so they can always be mapped to combinational hardware (adders etc) as dictated by the rhs expressions you find. The global control circuit is just the composition of the little circuit diagrams in the paper, also continuously extended as you parse new bits of the program. You can ignore optimisation, or extend the compiler to do (some of) it at compile time, or you can use third-party circuit optimisation tools post-compilation. The Xilinx mapping software will obviously do some of that job for free. The first job will be to decide how you want the Handel model to map onto the Forth syntax, and the PAR construct is likely to be the trickiest to accommodate." He said to start with the paper Compiling occam into Field-Programmable Gate Arrays at http://www.doc.ic.ac.uk/~wl/papers/fpl91a.pdf and there will hopefully soon be a PHForth - Parallel Hardware Forth. Should be about similar for parallel software as well running on different processors?? Then PSForth ? As far as I understand http://www.celoxica.com/ use it still internally for trading. As a tool rather than a product. It seems the problem has not changed for 15 years - how to promote a tools for hardware to be used by software guys. Reminds me of the C against Forth discussions ...
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| From | JUERGEN <epldfpga@aol.com> |
|---|---|
| Date | 2016-07-25 06:02 -0700 |
| Message-ID | <c4375e59-7973-469a-b6ef-b921d102e815@googlegroups.com> |
| In reply to | #49474 |
On Monday, July 25, 2016 at 1:57:17 PM UTC+1, JUERGEN wrote: > On Monday, July 25, 2016 at 3:29:28 AM UTC+1, rickman wrote: > > I wonder how hard it would be to write a Forth in VHDL? It would likely > > be as easy to do in non-synthesizable code as any other language. It > > might be a bit harder in synthesizable code. For one, the I/O would > > need to be constructed from scratch based on some hardware interface. > > The non-synthesizable code could just read from a file... I wonder if > > you can read from the console in VHDL? I've never tried that before. > > > > -- > > > > Rick C > > Forth to Gates - I had a discussion with Ian page last year - he developed C to gates in Oxford if I remember correctly. The product route: Handel-C - then ESL then Celoxica then Mentor. > If you can do C to Gates - Forth to Gates should be easier? > > He stated it should not be too difficult and said: > > "I am willing to give advice, however I’ve been out of academia for 14 years now - and haven’t written a program in any language in all that time! - so I am inevitably going to be rather out of touch with practical aspects which makes me unsure where I might be able to be of real help. > > The starting point for the other compiler builders I mentioned was the attached 1991 paper. You basically build a global hardware graph as you parse the input program. In the Handel model, all the rhs expressions are state-free, so they can always be mapped to combinational hardware (adders etc) as dictated by the rhs expressions you find. The global control circuit is just the composition of the little circuit diagrams in the paper, also continuously extended as you parse new bits of the program. You can ignore optimisation, or extend the compiler to do (some of) it at compile time, or you can use third-party circuit optimisation tools post-compilation. The Xilinx mapping software will obviously do some of that job for free. > > The first job will be to decide how you want the Handel model to map onto the Forth syntax, and the PAR construct is likely to be the trickiest to accommodate." > > He said to start with the paper Compiling occam into Field-Programmable Gate Arrays at http://www.doc.ic.ac.uk/~wl/papers/fpl91a.pdf and there will hopefully soon be a PHForth - Parallel Hardware Forth. Should be about similar for parallel software as well running on different processors?? Then PSForth ? > > As far as I understand http://www.celoxica.com/ use it still internally for trading. As a tool rather than a product. It seems the problem has not changed for 15 years - how to promote a tools for hardware to be used by software guys. Reminds me of the C against Forth discussions ... Just dug up another email, wher Ian said: In fact there was never anything proprietorial about the Handel approach and I deliberately published the core insights in 1991 and explicitly invited all comers to write their own hardware compilers in any language of their choice. A few did that, including Niklaus Wirth who did it in Oberon (http://www.inf.ethz.ch/personal/wirth/Oberon/286.pdf) and Paul Dunn at CSIRO who did it in occam. It would take rather little effort to knock up a Forth-based compiler, using an existing parser and compiler-compiler. The hard part of the trick of course is circuit optimisation, and that is hard both because it is NP hard and because it is hardware target dependent, so that will always require new work whenever a new hardware target is addressed.
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| From | Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> |
|---|---|
| Date | 2016-07-30 16:40 +0100 |
| Message-ID | <20160730164008.3f46a711@HP-6550b> |
| In reply to | #49474 |
On Mon, 25 Jul 2016 05:57:16 -0700 (PDT) JUERGEN <epldfpga@aol.com> wrote: > Forth to Gates - I had a discussion with Ian page last year - > he developed C to gates in Oxford if I remember correctly. The > product route: Handel-C - then ESL then Celoxica then Mentor. > If you can do C to Gates - Forth to Gates should be easier? > > He stated it should not be too difficult and said: > > "I am willing to give advice, however I’ve been out of > academia for 14 years now - and haven’t written a program in > any language in all that time! Apparently he has not missed much! Saw this in c.a.fpga fro someone who likely knows not to speak out of line: From: Kevin Neilson <kevin.neilson@xilinx.com> Subject: Mod-24: The State of High-Level Synthesis in 2016 Date: Fri, 22 Jul 2016 09:43:24 -0700 (PDT) User-Agent: G2/1.0 Newsgroups: comp.arch.fpga It's 2016 and I still have to write out most of my code at very low levels of abstraction like I did ten years ago. Whenever I hear about a new tool that supposedly converts C to gates, I don't even look into it, because I can't even get Verilog to synth properly. My latest example: I needed to reduce an 12-bit number, mod-24. [...] There are a further 20+ more posts exploring this problem. Jan Coombs --
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| From | JUERGEN <epldfpga@aol.com> |
|---|---|
| Date | 2016-08-01 08:58 -0700 |
| Message-ID | <d6136369-b4f1-44bf-9f96-7a24fe995b94@googlegroups.com> |
| In reply to | #49688 |
On Saturday, July 30, 2016 at 4:40:09 PM UTC+1, Jan Coombs wrote: > On Mon, 25 Jul 2016 05:57:16 -0700 (PDT) > JUERGEN <epldfpga@aol.com> wrote: > > > Forth to Gates - I had a discussion with Ian page last year - > > he developed C to gates in Oxford if I remember correctly. The > > product route: Handel-C - then ESL then Celoxica then Mentor. > > If you can do C to Gates - Forth to Gates should be easier? > > > > He stated it should not be too difficult and said: > > > > "I am willing to give advice, however I’ve been out of > > academia for 14 years now - and haven’t written a program in > > any language in all that time! > > Apparently he has not missed much! Saw this in c.a.fpga fro > someone who likely knows not to speak out of line: > > > From: Kevin Neilson <kevin.neilson@xilinx.com> > Subject: Mod-24: The State of High-Level Synthesis in 2016 > Date: Fri, 22 Jul 2016 09:43:24 -0700 (PDT) > User-Agent: G2/1.0 > Newsgroups: comp.arch.fpga > > It's 2016 and I still have to write out most of my code at very > low levels of abstraction like I did ten years ago. Whenever I > hear about a new tool that supposedly converts C to gates, I > don't even look into it, because I can't even get Verilog to > synth properly. > > My latest example: I needed to reduce an 12-bit number, mod-24. > > [...] > > > There are a further 20+ more posts exploring this problem. > > > Jan Coombs > -- Hardware people have a different head than SW people - This killed Embedded Solutions Limited - and probably Celoxica as SW supplier. Going back to roots of C to gates is like asking Chuck Moore how he would tackle it.
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| From | rickman <gnuarm@gmail.com> |
|---|---|
| Date | 2016-07-31 17:10 -0400 |
| Message-ID | <nnlpft$qgh$1@dont-email.me> |
| In reply to | #49474 |
On 7/25/2016 8:57 AM, JUERGEN wrote: > On Monday, July 25, 2016 at 3:29:28 AM UTC+1, rickman wrote: >> I wonder how hard it would be to write a Forth in VHDL? It would likely >> be as easy to do in non-synthesizable code as any other language. It >> might be a bit harder in synthesizable code. For one, the I/O would >> need to be constructed from scratch based on some hardware interface. >> The non-synthesizable code could just read from a file... I wonder if >> you can read from the console in VHDL? I've never tried that before. >> >> -- >> >> Rick C > > Forth to Gates - I had a discussion with Ian page last year - he developed C to gates in Oxford if I remember correctly. The product route: Handel-C - then ESL then Celoxica then Mentor. > If you can do C to Gates - Forth to Gates should be easier? > > He stated it should not be too difficult and said: > > "I am willing to give advice, however I’ve been out of academia for 14 years now - and haven’t written a program in any language in all that time! - so I am inevitably going to be rather out of touch with practical aspects which makes me unsure where I might be able to be of real help. The common HDL languages Verilog and VHDL both let you describe functionality which is then converted to gates by the tool (using a process that is not known to me). Another way that is supported in HDLs is instantiation, direct connection of primitives along with higher level blocks. Forth would be ideal for allowing this sort of constructs. If each function is defined in terms of lower level functions down to the primitives available in a given architecture device, it would be a snap to "execute" the top level design which would produce a flat design description or provide for a simulation capability. I guess I am describing a method that is a bit more "ad hoc" than current HDLs. So in some ways it may be a step backwards, but follows in the Forth philosophy of keeping it simple. -- Rick C
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| From | JUERGEN <epldfpga@aol.com> |
|---|---|
| Date | 2016-08-01 09:02 -0700 |
| Message-ID | <29ec7544-4160-4816-a58b-73c5005b25fd@googlegroups.com> |
| In reply to | #49708 |
On Sunday, July 31, 2016 at 10:10:23 PM UTC+1, rickman wrote: > On 7/25/2016 8:57 AM, JUERGEN wrote: > > On Monday, July 25, 2016 at 3:29:28 AM UTC+1, rickman wrote: > >> I wonder how hard it would be to write a Forth in VHDL? It would likely > >> be as easy to do in non-synthesizable code as any other language. It > >> might be a bit harder in synthesizable code. For one, the I/O would > >> need to be constructed from scratch based on some hardware interface. > >> The non-synthesizable code could just read from a file... I wonder if > >> you can read from the console in VHDL? I've never tried that before. > >> > >> -- > >> > >> Rick C > > > > Forth to Gates - I had a discussion with Ian page last year - he developed C to gates in Oxford if I remember correctly. The product route: Handel-C - then ESL then Celoxica then Mentor. > > If you can do C to Gates - Forth to Gates should be easier? > > > > He stated it should not be too difficult and said: > > > > "I am willing to give advice, however I’ve been out of academia for 14 years now - and haven’t written a program in any language in all that time! - so I am inevitably going to be rather out of touch with practical aspects which makes me unsure where I might be able to be of real help. > > The common HDL languages Verilog and VHDL both let you describe > functionality which is then converted to gates by the tool (using a > process that is not known to me). > > Another way that is supported in HDLs is instantiation, direct > connection of primitives along with higher level blocks. Forth would be > ideal for allowing this sort of constructs. If each function is defined > in terms of lower level functions down to the primitives available in a > given architecture device, it would be a snap to "execute" the top level > design which would produce a flat design description or provide for a > simulation capability. > > I guess I am describing a method that is a bit more "ad hoc" than > current HDLs. So in some ways it may be a step backwards, but follows > in the Forth philosophy of keeping it simple. > > -- > > Rick C Optimising the outcome is step 2. Forth would achieve a fast implementation. If the result fits into the chosen FPGA - done. Or you might use this as the starting point for optimisation - using standard tools - or the PFO - the now secret Parallel Forth Optimiser.
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| From | Ilya Tarasov <ilya74.tarasov@gmail.com> |
|---|---|
| Date | 2016-07-29 05:42 -0700 |
| Message-ID | <5cc4c0cb-9df1-4056-a8e2-f4511fc8b7d5@googlegroups.com> |
| In reply to | #49421 |
понедельник, 25 июля 2016 г., 5:29:28 UTC+3 пользователь rickman написал: > I wonder how hard it would be to write a Forth in VHDL? It would likely > be as easy to do in non-synthesizable code as any other language. It > might be a bit harder in synthesizable code. For one, the I/O would > need to be constructed from scratch based on some hardware interface. > The non-synthesizable code could just read from a file... I wonder if > you can read from the console in VHDL? I've never tried that before. Forth in VHDL looks perspective enough from the VHDL designers point of view. There are several point where embedded interpreter may be useful: 1. Embedded CPUs code compiling, both for modelling and implementing. Now memory initialization usually performed by VHDL initialization vector (simpler but worse) or external text file, loaded with TextIO package functions. Having source code inside VHDL greatly improves readability. Also applicable for FSMs. 2. DSP algorithms with heavy math support. Same problems as previous - external tool must conform to actual VHDL code, readability of embedded text is higher. Im not sure console is absolutely needed. External file or just strings inside VHDL is enough to work.
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