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Delay Line Memory

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  Delay Line Memory "Charles Richmond" <numerist@aquaporin4.com> - 2016-02-16 15:21 -0600
    Re: Delay Line Memory Dave Garland <dave.garland@wizinfo.com> - 2016-02-16 15:41 -0600
    Re: Delay Line Memory David Wade <dave.g4ugm@gmail.com> - 2016-02-16 22:18 +0000
    Re: Delay Line Memory Dan Espen <despen@verizon.net> - 2016-02-16 17:36 -0500
    Re: Delay Line Memory Lawrence Statton <lawrence@senguio.mx> - 2016-02-16 16:57 -0600
    Re: Delay Line Memory bert <bert.hutchings@btinternet.com> - 2016-02-16 15:08 -0800
      Re: Delay Line Memory Bob Eager <news0006@eager.cx> - 2016-02-17 01:31 +0000
      Re: Delay Line Memory Charlie Gibbs <cgibbs@kltpzyxm.invalid> - 2016-02-17 03:42 +0000
    Re: Delay Line Memory Morten Reistad <first@last.name.invalid> - 2016-02-17 00:25 +0100
      Re: Delay Line Memory Elliott Roper <nospam@yrl.co.uk> - 2016-02-17 14:03 +0000
    Re: Delay Line Memory Anonymous <no_email@invalid.invalid> - 2016-02-17 00:14 +0000
      Re: Delay Line Memory Quadibloc <jsavard@ecn.ab.ca> - 2016-02-17 11:46 -0800
        Re: Delay Line Memory jhhaynes@earthlink.net - 2016-02-17 18:18 -0800
        Re: Delay Line Memory David Wade <dave.g4ugm@gmail.com> - 2016-02-18 09:44 +0000
    Re: Delay Line Memory hancock4@bbs.cpcn.com - 2016-02-16 16:43 -0800
      Re: Delay Line Memory Anonymous <no_email@invalid.invalid> - 2016-02-17 01:24 +0000
      Re: Delay Line Memory Peter Flass <peter_flass@yahoo.com> - 2016-02-16 18:52 -0700
        Re: Delay Line Memory Michael Black <et472@ncf.ca> - 2016-02-16 22:19 -0500
        Re: Delay Line Memory JimP <solosam90@gmail.com> - 2016-02-17 11:34 -0600
      Re: Delay Line Memory Dave Garland <dave.garland@wizinfo.com> - 2016-02-16 20:06 -0600
      Re: Delay Line Memory Lawrence Statton <lawrence@senguio.mx> - 2016-02-16 20:23 -0600
      Re: Delay Line Memory "hgww" <hgww@gmail.com> - 2016-02-17 14:35 +1100
      Re: Delay Line Memory Charlie Gibbs <cgibbs@kltpzyxm.invalid> - 2016-02-17 04:17 +0000
        Re: Delay Line Memory "Charles Richmond" <numerist@aquaporin4.com> - 2016-02-18 17:14 -0600
          Re: Delay Line Memory Lawrence Statton <lawrence@senguio.mx> - 2016-02-18 19:27 -0600
            Re: Delay Line Memory Charlie Gibbs <cgibbs@kltpzyxm.invalid> - 2016-02-19 04:14 +0000
            Re: Delay Line Memory Michael Black <et472@ncf.ca> - 2016-02-19 19:07 -0500
    Re: Delay Line Memory Bob Eager <news0006@eager.cx> - 2016-02-17 01:30 +0000
      Re: Delay Line Memory "Joe Morris" <j.c.morris@verizon.net> - 2016-02-17 19:11 -0500
        Re: Delay Line Memory Michael Black <et472@ncf.ca> - 2016-02-17 23:13 -0500
          Re: Delay Line Memory Jon Elson <elson@pico-systems.com> - 2016-02-17 22:25 -0600
          Re: Delay Line Memory isw <isw@witzend.com> - 2016-02-17 23:16 -0800
            Re: Delay Line Memory Jon Elson <elson@pico-systems.com> - 2016-02-18 12:01 -0600
              Re: Delay Line Memory Jon Elson <elson@pico-systems.com> - 2016-02-18 12:10 -0600
              Re: Delay Line Memory Lawrence Statton <lawrence@senguio.mx> - 2016-02-18 13:46 -0600
              Re: Delay Line Memory Michael Black <et472@ncf.ca> - 2016-02-19 19:13 -0500
          Re: Delay Line Memory Quadibloc <jsavard@ecn.ab.ca> - 2016-02-18 04:49 -0800
            Re: Delay Line Memory Michael Black <et472@ncf.ca> - 2016-02-19 19:21 -0500
          Re: Delay Line Memory Quadibloc <jsavard@ecn.ab.ca> - 2016-02-18 04:51 -0800
            Re: Delay Line Memory Michael Black <et472@ncf.ca> - 2016-02-19 19:16 -0500
    Re: Delay Line Memory Peter Flass <peter_flass@yahoo.com> - 2016-02-16 18:52 -0700
      Re: Delay Line Memory "Charles Richmond" <numerist@aquaporin4.com> - 2016-02-19 20:50 -0600
        Re: Delay Line Memory Ahem A Rivet's Shot <steveo@eircom.net> - 2016-02-20 06:31 +0000
    Re: Delay Line Memory G. <gerry77@no.spam.mail.com> - 2016-02-17 04:08 +0100
    Re: Delay Line Memory Stan Barr <plan.b@bluesomatic.org> - 2016-02-17 08:19 +0000
      Re: Delay Line Memory Jon Elson <jmelson@wustl.edu> - 2016-02-17 14:57 -0600
      Re: Delay Line Memory "Charles Richmond" <numerist@aquaporin4.com> - 2016-02-19 20:43 -0600
        Re: Delay Line Memory isw <isw@witzend.com> - 2016-02-19 22:13 -0800
        Re: Delay Line Memory Stan Barr <plan.b@bluesomatic.org> - 2016-02-20 08:17 +0000
        Re: Delay Line Memory Lawrence Statton <lawrence@senguio.mx> - 2016-02-20 09:17 -0600
          Re: Delay Line Memory Lawrence Statton <lawrence@senguio.mx> - 2016-02-20 09:20 -0600
        Re: Delay Line Memory Quadibloc <jsavard@ecn.ab.ca> - 2016-02-20 18:49 -0800
          Re: Delay Line Memory isw <isw@witzend.com> - 2016-02-20 21:06 -0800
    Re: Delay Line Memory jhhaynes@earthlink.net - 2016-02-17 18:23 -0800
      Re: Delay Line Memory isw <isw@witzend.com> - 2016-02-17 23:06 -0800

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#159549

hancock4@bbs.cpcn.com writes:
> Question:  when IBM introduced its PC, it had up to 640k of memory.

Not quite.  There was a hole in the address space that big, but the most
memory you could order the first edition machine was 64K.  The second
rev of the board took 64k x 1 chips, so you could get 256K on the motherboard.

It was a few months or a year before other manufacturers sold memory
expansion (often coupled with a parallel port and a RTC and marketed as
a "Combo Board") that could add another 256K.

> I think smaller amounts were available, with a cheaper price.  Did
> customers actually want to save a few bucks and go for the cheaper
> and smaller PC?

By "few bucks" you mean "Several hundred", right?

At the time of the PC's release, 256K of memory would set you back about
$500.

> (To me, it seemed people couldn't wait for expanded
> and extended memory to come out so the PC could get up to 1 meg and
> even beyond, so it's hard to believe people would accept less than
> 640k.)



--NK1G

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#159559

<hancock4@bbs.cpcn.com> wrote in message 
news:a96bdf8d-4419-477d-a3d5-6eefc4772139@googlegroups.com...
> On Tuesday, February 16, 2016 at 4:21:16 PM UTC-5, Charles Richmond wrote:
>> Yesterday I saw a video on YouTube about a delay line memory device.  It 
>> did
>> *not* use mercury or any liquid to hold and circulate the memory 
>> contents.
>> Instead it had a *wire*!!!  The wire was physically twisted at one end ot
>> input the bit.  The other end "decoded" the bit and also re-circulated 
>> the
>> bit.
>
> As someone else mentioned, there was probably some sort of electrical
> component to receive and then pass on each bit.  The delay in doing so
> allowed for the memory.
>
> Old issues of C&A had ads for "pulse transformers", which may have been
> used for delay line memory.
>
> Today, it's hard to believe that core memory was once so expensive that
> cheaper alternatives were sought.
>
> When IBM introduced the 650, which used a magnetic drum for memory,
> I think core was available, but the drum was cheaper.  Later variants
> of the 650 had a tiny bit of core for buffers.  As just discussed,
> the low end 1401 had only 1,400 characters of memory in it.
>
> Question:  when IBM introduced its PC, it had up to 640k of memory.
> I think smaller amounts were available, with a cheaper price.  Did
> customers actually want to save a few bucks and go for the cheaper
> and smaller PC?

Yes, some did.

> (To me, it seemed people couldn't wait for expanded
> and extended memory to come out so the PC could get up to 1 meg and
> even beyond,

But not everyone did that.

> so it's hard to believe people would accept less than 640k.)

Plenty did. 

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#159568

On 2016-02-17, hancock4@bbs.cpcn.com <hancock4@bbs.cpcn.com> wrote:

> Question:  when IBM introduced its PC, it had up to 640k of memory.
> I think smaller amounts were available, with a cheaper price.  Did
> customers actually want to save a few bucks and go for the cheaper
> and smaller PC?  (To me, it seemed people couldn't wait for expanded
> and extended memory to come out so the PC could get up to 1 meg and
> even beyond, so it's hard to believe people would accept less than 640k.)

Memory was expensive.  Lots of IBM PCs and clones had 256K or less.
(Why should they have more memory than the mainframe?)  It's easy
to forget how expensive things were back then.  Around the time the
IBM PC came out, I was doing a regular Friday pilgrimage to the
local Heathkit store to spend $16 on another 2016 static RAM chip,
building up my S-100 memory board 2K at a time.  It was over 5 years
after the introduction of the IBM PC that I laid out $700 for a 2MB
memory expansion for my Amiga 1000.  Then I had enough space to set
up a bootable RAM disk so I could get some speed without spending
the $2000 that a hard drive cost back then.

-- 
/~\  cgibbs@kltpzyxm.invalid (Charlie Gibbs)
\ /  I'm really at ac.dekanfrus if you read it the right way.
 X   Top-posted messages will probably be ignored.  See RFC1855.
/ \  HTML will DEFINITELY be ignored.  Join the ASCII ribbon campaign!

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#159732

"Charlie Gibbs" <cgibbs@kltpzyxm.invalid> wrote in message 
news:na0s990oaf@news3.newsguy.com...
> On 2016-02-17, hancock4@bbs.cpcn.com <hancock4@bbs.cpcn.com> wrote:
>
>> Question:  when IBM introduced its PC, it had up to 640k of memory.
>> I think smaller amounts were available, with a cheaper price.  Did
>> customers actually want to save a few bucks and go for the cheaper
>> and smaller PC?  (To me, it seemed people couldn't wait for expanded
>> and extended memory to come out so the PC could get up to 1 meg and
>> even beyond, so it's hard to believe people would accept less than 640k.)
>
> Memory was expensive.  Lots of IBM PCs and clones had 256K or less.
> (Why should they have more memory than the mainframe?)  It's easy
> to forget how expensive things were back then.  Around the time the
> IBM PC came out, I was doing a regular Friday pilgrimage to the
> local Heathkit store to spend $16 on another 2016 static RAM chip,
> building up my S-100 memory board 2K at a time.  It was over 5 years
> after the introduction of the IBM PC that I laid out $700 for a 2MB
> memory expansion for my Amiga 1000.  Then I had enough space to set
> up a bootable RAM disk so I could get some speed without spending
> the $2000 that a hard drive cost back then.
>

I remember in 1980, seeing an advertisement for a 64k memory board for the 
S-100 bus.  This board had 32 RAM chips, each was 16k x 1 bits, plus 
associated interface and addressing chips.  And the board was *only* $1000 
US !!!   I was amazed that much memory could be had so cheaply!!!

Back in 1986, I bought a 20 megabyte 3 1/2" hard drive in a "shoebox" that 
contained the power supply and hard disk interface card to the disk could be 
connect to an Atari ST.  I think I paid $600 US for it, but it may have been 
more like $800. Now this drive held only 20 megs!!!

I later replaced the 20 megabyte 3 1/2" drive mech with a Seagate ST-251 40 
megabyte drive mech that was "self-parking".  The Seagate drive was great 
because it was so *noisy*!!! You felt like accessing your information took 
real work from the hard drive!!!

-- 

numerist at aquaporin4 dot com

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#159746

"Charles Richmond" <numerist@aquaporin4.com> writes:
> I remember in 1980, seeing an advertisement for a 64k memory board for
> the S-100 bus.  This board had 32 RAM chips, each was 16k x 1 bits,
> plus associated interface and addressing chips.  And the board was
> *only* $1000 US !!!   I was amazed that much memory could be had so
> cheaply!!!

In fairness - most S100 memory boards used static memory for "good and
sufficient reason" ("D-Ram timing is *hard*" quoth an engineer friend of
mine), and perhaps because some of the earliest dynamic boards were
Unbearably Badly Engineered, buyers were skeptical of them.  I had one
stuffed to the gills with 2114 (1K x 4 in an 18-pin DIP) that was 32K,
and was hot as a pistol.  Those chips were close to half a watt each,
and sticking 64 of them in a board sucked a few amps off the 8V bus.  It
had two LM323 (TO3 five volt regulator rated for 3A), and each of those
had a honkin' huge shunt resistor to keep package dissipation down.

Good times...

A friend of mine had a box with 7 8K boards, that used 64 pieces of good
old 2102, with the same "WW resistor over the regulator" shunt trick,
and when he replaced the memory chips with 21L02, he didn't know to cut
the resistor off.  He came by my lab, and we replaced the chips *again*,
and this time I explained "three terminal regulators can only source
current, they can't sink -- if your load current goes DOWN, you will
need to increase the shut resistance, or in this case, remove it
entirely -- the regulator can easily supply the load by itself"

--NK1G

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#159756

On 2016-02-19, Lawrence Statton <lawrence@senguio.mx> wrote:

> "Charles Richmond" <numerist@aquaporin4.com> writes:
>
>> I remember in 1980, seeing an advertisement for a 64k memory board for
>> the S-100 bus.  This board had 32 RAM chips, each was 16k x 1 bits,
>> plus associated interface and addressing chips.  And the board was
>> *only* $1000 US !!!   I was amazed that much memory could be had so
>> cheaply!!!
>
> In fairness - most S100 memory boards used static memory for "good and
> sufficient reason" ("D-Ram timing is *hard*" quoth an engineer friend of
> mine), and perhaps because some of the earliest dynamic boards were
> Unbearably Badly Engineered, buyers were skeptical of them.  I had one
> stuffed to the gills with 2114 (1K x 4 in an 18-pin DIP) that was 32K,
> and was hot as a pistol.  Those chips were close to half a watt each,
> and sticking 64 of them in a board sucked a few amps off the 8V bus.  It
> had two LM323 (TO3 five volt regulator rated for 3A), and each of those
> had a honkin' huge shunt resistor to keep package dissipation down.
>
> Good times...

Yup.  When I first built my IMSAI I had two RAM-4A boards, each with
4K worth of 2102s.  The regulators ran hot.  I replaced it with a
64K static RAM board which I bought with 16K and gradually worked
my way up to 62K, one 2016 at a time (half of the other 2K was for
the 2708 holding the boot code and BIOS, and the other for scratch
RAM for the BIOS).  Even fully loaded, the board ran cool.

-- 
/~\  cgibbs@kltpzyxm.invalid (Charlie Gibbs)
\ /  I'm really at ac.dekanfrus if you read it the right way.
 X   Top-posted messages will probably be ignored.  See RFC1855.
/ \  HTML will DEFINITELY be ignored.  Join the ASCII ribbon campaign!

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#159866

On Thu, 18 Feb 2016, Lawrence Statton wrote:

> "Charles Richmond" <numerist@aquaporin4.com> writes:
>> I remember in 1980, seeing an advertisement for a 64k memory board for
>> the S-100 bus.  This board had 32 RAM chips, each was 16k x 1 bits,
>> plus associated interface and addressing chips.  And the board was
>> *only* $1000 US !!!   I was amazed that much memory could be had so
>> cheaply!!!
>
> In fairness - most S100 memory boards used static memory for "good and
> sufficient reason" ("D-Ram timing is *hard*" quoth an engineer friend of
> mine), and perhaps because some of the earliest dynamic boards were
> Unbearably Badly Engineered, buyers were skeptical of them.  I had one
> stuffed to the gills with 2114 (1K x 4 in an 18-pin DIP) that was 32K,
> and was hot as a pistol.  Those chips were close to half a watt each,
> and sticking 64 of them in a board sucked a few amps off the 8V bus.  It
> had two LM323 (TO3 five volt regulator rated for 3A), and each of those
> had a honkin' huge shunt resistor to keep package dissipation down.
>
Dynamic RAM was a new thing for a lot of the people creating the very 
early home computers.  I think the Altair board used RC timing for 
something on their dynamic RAM board, and apparently that gave a lot of 
trouble.  It gave a bad name to dynamic RAM, so others avoided it, at 
least for a while.

I ended up with a stray Processor Technology dynamic RAM board, I think 
it's 16K, I got it about 1990 and no computer for it.  I gather it was 
okay, but when I checked the ads for this board, it was something like 
$695 in 1976 or so.

But somehow things improved, either people got better, or they just 
overcame the bias against dynamic RAM.  The Apple II of course made good 
use of it, including the ability to upgrade when the higher density RAM 
came along.  So did the TRS-80 that year, though I have a vague memory 
that their expansion RAM didn't work so well, in part because it was in a 
separate box.  At some point it became easier and cheaper to use dynamic 
RAM unless you only needed small amounts.  My OSI Superboard had only 
space for 8K of RAM, so there was no sense in going dynamic.

I also remember when 2K by 8 static RAM came along, in 24pin packages so 
they could interchange with eproms. Godbout soon came out with a board 
that I think was 64K, still a lot of ICs on that board, but not as bad as 
lower density RAM and since it was CMOS, suddenly the issue of power draw 
was no longer there.

The odd thing is, those CMOS static RAMs became even denser, but by that 
point dynamic RAM was the way, so we generally didn't see anyone using the 
denser CMOS static ram in "home computers".

Though I remember 15 or 20 years ago, people suggesting grabbing cache RAM 
off "old" motherboards for projects, 32K RAM in a thin 24 or so pin 
package, one or two ICs good enough for a "controller" type project.

   Michael

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#159537

On Tue, 16 Feb 2016 15:21:14 -0600, Charles Richmond wrote:

> Yesterday I saw a video on YouTube about a delay line memory device.  It
> did *not* use mercury or any liquid to hold and circulate the memory
> contents. Instead it had a *wire*!!!  The wire was physically twisted at
> one end ot input the bit.  The other end "decoded" the bit and also
> re-circulated the bit.
> 
> https://www.youtube.com/watch?v=N9cUbYII5RY
> 
> 
> I'd *never* heard of anything like this!  Is anyone here familiar with
> this type of delay line memory???  What machines used this???

Dunno, but the EDSAC rebuild in the UK is using nickel delay lines 
instead of the original mercury. This is on grounds of cost, as well as 
health and safety.

 http://www.tnmoc.org/special-projects/edsac/recreating-edsac



-- 
Using UNIX since v6 (1975)...

Use the BIG mirror service in the UK:
 http://www.mirrorservice.org

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#159620

 Charles Richmond wrote:

> Yesterday I saw a video on YouTube about a delay line memory device.  It
> did *not* use mercury or any liquid to hold and circulate the memory
> contents. Instead it had a *wire*!!!  The wire was physically twisted at
> one end ot input the bit.  The other end "decoded" the bit and also
> re-circulated the bit.

> https://www.youtube.com/watch?v=N9cUbYII5RY

> I'd *never* heard of anything like this!  Is anyone here familiar with
> this type of delay line memory???  What machines used this???

The IBM 2260 CRT terminal, which was introduced in 1964, was a text-only 
device (with 240, 480, or 960 character display capacity) that *really* met 
the definition of a "dumb terminal"...its display was merely a pattern 
controlled by the 2848 Control Unit, essentially similar to the video 
circuitry in a traditional analog television set.

This is on-topic because the 2848 used an acoustic delay line - twisted 
wire - to hold the text to be shown on each attached 2260 display head. 
There was one delay line for each attached head; my recollection is that 
each delay line was housed in a metal can about 10" square by 3/4" thick.

An interesting oddity about the 2848 was that it used a magnetic core matrix 
to generate the light/dark pattern of dots that formed characters on the 
displays. You could look at the matrix and easily see many of the glyphs.

Wikipedia has an article on the 2260, including links to some documents 
(including the 2848 FE manual) on Bitsavers.

Joe 

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#159636

On Wed, 17 Feb 2016, Joe Morris wrote:

> Charles Richmond wrote:
>
>> Yesterday I saw a video on YouTube about a delay line memory device.  It
>> did *not* use mercury or any liquid to hold and circulate the memory
>> contents. Instead it had a *wire*!!!  The wire was physically twisted at
>> one end ot input the bit.  The other end "decoded" the bit and also
>> re-circulated the bit.
>
>> https://www.youtube.com/watch?v=N9cUbYII5RY
>
>> I'd *never* heard of anything like this!  Is anyone here familiar with
>> this type of delay line memory???  What machines used this???
>
> The IBM 2260 CRT terminal, which was introduced in 1964, was a text-only
> device (with 240, 480, or 960 character display capacity) that *really* met
> the definition of a "dumb terminal"...its display was merely a pattern
> controlled by the 2848 Control Unit, essentially similar to the video
> circuitry in a traditional analog television set.
>
> This is on-topic because the 2848 used an acoustic delay line - twisted
> wire - to hold the text to be shown on each attached 2260 display head.
> There was one delay line for each attached head; my recollection is that
> each delay line was housed in a metal can about 10" square by 3/4" thick.
>
> An interesting oddity about the 2848 was that it used a magnetic core matrix
> to generate the light/dark pattern of dots that formed characters on the
> displays. You could look at the matrix and easily see many of the glyphs.
>
> Wikipedia has an article on the 2260, including links to some documents
> (including the 2848 FE manual) on Bitsavers.
>
And for some reason, when solid state memory came along, it wsa in the 
form of long shift registers, though I'm not sure if that was the only 
option or in parallel with "random access memory".  I know about 1974, Don 
Lancaster's first "TV Typewriter" was said to use it, and slow scan tv 
converters for amateur radio used them.

I don't know whether somebody hadn't made a leap to memory directly 
addressable or there was some reason to go with long shift registers.

But of course, like the delay lines, you had to keep the bits circulating, 
and you could only get to each of the bytes by stepping through all that 
came before.

   Michael

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#159638

Michael Black wrote:


> And for some reason, when solid state memory came along, it wsa in the
> form of long shift registers, though I'm not sure if that was the only
> option or in parallel with "random access memory".  I know about 1974, Don
> Lancaster's first "TV Typewriter" was said to use it, and slow scan tv
> converters for amateur radio used them.
I cloned a Beehive terminal that used this in 1977 or so.  Horrible wire-
wrapped monster, but it worked.  The memory used charge coupled devices, so 
the actual memory chips had very little "active" circuitry on them.  Mostly 
just a long string of MOS capacitors with drive lines.  I guess they had a 
sense amplifier at the output end.

Jon

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#159647

In article <alpine.LNX.2.02.1602172309580.24250@darkstar.example.org>,
 Michael Black <et472@ncf.ca> wrote:

> On Wed, 17 Feb 2016, Joe Morris wrote:
> 
> > Charles Richmond wrote:
> >
> >> Yesterday I saw a video on YouTube about a delay line memory device.  It
> >> did *not* use mercury or any liquid to hold and circulate the memory
> >> contents. Instead it had a *wire*!!!  The wire was physically twisted at
> >> one end ot input the bit.  The other end "decoded" the bit and also
> >> re-circulated the bit.
> >
> >> https://www.youtube.com/watch?v=N9cUbYII5RY
> >
> >> I'd *never* heard of anything like this!  Is anyone here familiar with
> >> this type of delay line memory???  What machines used this???
> >
> > The IBM 2260 CRT terminal, which was introduced in 1964, was a text-only
> > device (with 240, 480, or 960 character display capacity) that *really* met
> > the definition of a "dumb terminal"...its display was merely a pattern
> > controlled by the 2848 Control Unit, essentially similar to the video
> > circuitry in a traditional analog television set.
> >
> > This is on-topic because the 2848 used an acoustic delay line - twisted
> > wire - to hold the text to be shown on each attached 2260 display head.
> > There was one delay line for each attached head; my recollection is that
> > each delay line was housed in a metal can about 10" square by 3/4" thick.
> >
> > An interesting oddity about the 2848 was that it used a magnetic core matrix
> > to generate the light/dark pattern of dots that formed characters on the
> > displays. You could look at the matrix and easily see many of the glyphs.
> >
> > Wikipedia has an article on the 2260, including links to some documents
> > (including the 2848 FE manual) on Bitsavers.
> >
> And for some reason, when solid state memory came along, it wsa in the 
> form of long shift registers, though I'm not sure if that was the only 
> option or in parallel with "random access memory".  I know about 1974, Don 
> Lancaster's first "TV Typewriter" was said to use it, and slow scan tv 
> converters for amateur radio used them.
> 
> I don't know whether somebody hadn't made a leap to memory directly 
> addressable or there was some reason to go with long shift registers.

A serial shift register is just a long string of D-type flip-flops. No 
real "addressing" needed, just a counter. Plus, in the days when a lot 
of chips were laid out *by hand*, a very simple step-and-repeat was very 
appealing.

Isaac

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#159698

isw wrote:


> 
> A serial shift register is just a long string of D-type flip-flops. No
> real "addressing" needed, just a counter. Plus, in the days when a lot
> of chips were laid out *by hand*, a very simple step-and-repeat was very
> appealing.
Actually, creating a full-screen (1920 bytes) memory out of D-flops would be 
prohibitive.  Assuming you only needed 6 bits per character, that is still
11520 bits, or 1920 chips of 6-wide D-flops.  When these things were built, 
2 FF/chip was the max, so that would be 5000 IC packages!  Obviously, not 
practical.

The Beehive monster I cloned used the 1404 chip, available from Intel and 
AMD.  1024 bits by CCD bucket-brigade technology.  It needed only 14 of 
these chips to hold 2048 7-bit characters.  (the screen only displayed 1920 
in that particular unit.)

Jon

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#159700

Jon Elson wrote:


> The Beehive monster I cloned used the 1404 chip, available from Intel and
> AMD.  1024 bits by CCD bucket-brigade technology.  It needed only 14 of
> these chips to hold 2048 7-bit characters.  (the screen only displayed
> 1920 in that particular unit.)
And, looking it up, they apparently were NOT CCDs, although from the outside 
you really couldn't tell that, by the way they worked.  Seems the scheme was 
a string of "sticky inverters" with capacitors at the input, and 
transmission gates between stages.  They needed a 2-phase clock.

Jon

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#159713

Jon Elson <elson@pico-systems.com> writes:

> isw wrote:
>
>
>> 
>> A serial shift register is just a long string of D-type flip-flops. No
>> real "addressing" needed, just a counter. Plus, in the days when a lot
>> of chips were laid out *by hand*, a very simple step-and-repeat was very
>> appealing.
> Actually, creating a full-screen (1920 bytes) memory out of D-flops would be 
> prohibitive.  Assuming you only needed 6 bits per character, that is still
> 11520 bits, or 1920 chips of 6-wide D-flops.  When these things were built, 
> 2 FF/chip was the max, so that would be 5000 IC packages!  Obviously, not 
> practical.
>

Well - building a memory out of discrete 74S74s would be painful, but
the static S/R memory could do that in a few square mils of real estate,
and did exactly that.  (And, yes, static S/R was marginally more costly
than dynamic S/R, but was stable with no clock, which makes them
particularly well suited for terminals) ...

It is somewhat noteworthy, if you go look at some of the databooks from
the early 70s, that S/R memories came in such convenient sizes as 80 x
1, 80 x 2 etc.  Many of these were available in convenient TO-5 packages,
so as not to frighten the engineering team with those new-fangled DIPs
:) 

I don't remember anyone making anything larger than twin chains, but
that could be bit-rot.  

A dozen pieces of 960 x 1 for the page buffer, and a half-dozen 80x1 for
the line buffer is all the memory a full 80x24 terminal would need.

--NK1G

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#159867

On Thu, 18 Feb 2016, Jon Elson wrote:

> isw wrote:
>
>
>>
>> A serial shift register is just a long string of D-type flip-flops. No
>> real "addressing" needed, just a counter. Plus, in the days when a lot
>> of chips were laid out *by hand*, a very simple step-and-repeat was very
>> appealing.
> Actually, creating a full-screen (1920 bytes) memory out of D-flops would be
> prohibitive.  Assuming you only needed 6 bits per character, that is still
> 11520 bits, or 1920 chips of 6-wide D-flops.  When these things were built,
> 2 FF/chip was the max, so that would be 5000 IC packages!  Obviously, not
> practical.
>
There were "quad latches" like the 7475 to go between counters and BCD to 
7 segment decoders, needed when the counter was otherwise always counting. 
I can't remember if the pinout allowed the four flip-flops to be used as a 
shift register, but if it could, that would improve density 2:1.  Later 
(but of course by then nobody was using shift registers for memory), you 
could get 8 latches in the same package, to latch an 8bit bus.

    Michael

> The Beehive monster I cloned used the 1404 chip, available from Intel and
> AMD.  1024 bits by CCD bucket-brigade technology.  It needed only 14 of
> these chips to hold 2048 7-bit characters.  (the screen only displayed 1920
> in that particular unit.)
>
> Jon
>

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#159661

On Wednesday, February 17, 2016 at 9:08:09 PM UTC-7, Michael Black wrote:

> And for some reason, when solid state memory came along, it wsa in the 
> form of long shift registers, though I'm not sure if that was the only 
> option or in parallel with "random access memory".

For a short time, although there were static random access memory chips also available, they had a limited capacity, and the long shift registers were the only chips that could hold a full 1,024 bits on a single chip.

Or so I thought, but looking it up:

Intel 1402/3/4 shift register - 1970
Intel 1103 DRAM - 1970
Intel 2102 SRAM - 1972

So while 1K static RAMs came 2 years later, 1K dynamic RAMs and 1K shift 
registers were at least approximately contemporaneous. But a dynamic RAM would 
require significantly more support circuitry, so if you could get away with a 
shift register - say if you were designing a video terminal or "TV Typewriter" 
(vide Don Lancaster's famous Cookbook) - you would. No doubt they were cheaper 
too.

John Savard

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#159869

On Thu, 18 Feb 2016, Quadibloc wrote:

> On Wednesday, February 17, 2016 at 9:08:09 PM UTC-7, Michael Black wrote:
>
>> And for some reason, when solid state memory came along, it wsa in the
>> form of long shift registers, though I'm not sure if that was the only
>> option or in parallel with "random access memory".
>
> For a short time, although there were static random access memory chips also available, they had a limited capacity, and the long shift registers were the only chips that could hold a full 1,024 bits on a single chip.
>
> Or so I thought, but looking it up:
>
> Intel 1402/3/4 shift register - 1970
> Intel 1103 DRAM - 1970
> Intel 2102 SRAM - 1972
>
> So while 1K static RAMs came 2 years later, 1K dynamic RAMs and 1K shift
> registers were at least approximately contemporaneous. But a dynamic RAM would
> require significantly more support circuitry, so if you could get away with a
> shift register - say if you were designing a video terminal or "TV Typewriter"
> (vide Don Lancaster's famous Cookbook) - you would. No doubt they were cheaper
> too.
>
That's the thing.  It was available "surplus" (I have no idea if that 
actually meant "no longer needed" or it was just a distribution channel) 
and thus "cheap".  Right at that point, there wasn't much need for large 
storage in hobbyist circles, but if you needed it, you ended up using 
those long shift registers.  I can't remember if I mentioned amateur radio 
slow scan TV in my previous post, but that was using it up too around 
1974, about the only thing besides that TV typewriter that made use of RAM 
(it was a blink before microprocessors took off).  I remember talk of one 
SSTV scan converter, and a dismissal "because now you can't get the long 
shift registers for it", which I assumed meant "the surplus stock dried 
up".

   Michael

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#159662

On Wednesday, February 17, 2016 at 9:08:09 PM UTC-7, Michael Black wrote:

> But of course, like the delay lines, you had to keep the bits circulating, 

That's not true of shift registers in general - although it _was_ true of the 
Intel 1402 et al, as it was a _dynamic_ shift register. So it could have a single 
transistor per bit instead of a whole flip-flop.

John Savard

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#159868

On Thu, 18 Feb 2016, Quadibloc wrote:

> On Wednesday, February 17, 2016 at 9:08:09 PM UTC-7, Michael Black wrote:
>
>> But of course, like the delay lines, you had to keep the bits circulating,
>
> That's not true of shift registers in general - although it _was_ true of the
> Intel 1402 et al, as it was a _dynamic_ shift register. So it could have a single
> transistor per bit instead of a whole flip-flop.
>
Sorry.  I was speaking in terms of retrieving a given bit.  I'm talking 
long shift registers, you had to circulate the bit to the output in order 
to make use of it, and then have the bit fed back into the input so it 
wouldn't be forgotten by the shift register memory.

   Michael

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