Re: Register windows

From	Niklas Holsti <niklas.holsti@tidorum.invalid>
Newsgroups	comp.arch
Subject	Re: Register windows
Date	2025-07-18 23:17 +0300
Organization	Tidorum Ltd
Message-ID	<mdvoejFmi67U1@mid.individual.net> (permalink)
References	(17 earlier) <1059tti$16il5$1@dont-email.me> <f19813b55e635188c81f989aa63f0462@www.novabbs.org> <jwvldomkdua.fsf-monnier+comp.arch@gnu.org> <mdv6hmFheagU1@mid.individual.net> <jwvfretfs4u.fsf-monnier+comp.arch@gnu.org>

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On 2025-07-18 18:29, Stefan Monnier wrote:
>> The Mill "belt" (I assume this is what you call the "stack") corresponds to
>> the "first-class registers": all computations take operands from the belt
>> and push results to the belt. When a function is called, it sees a fresh
>> belt with only its "in" arguments; when the function returns, it leaves its
>> "out" results pushed on the belt that the caller sees.
> 
> That's right.  The belt is the closest that the Mill has to "first-class
> registers", tho in a sense it addresses elements of the forwarding
> network more than "registers".

Yes. Values on the belt do not stay at fixed addresses ("register 
numbers", "names") but move to new addresses (larger offsets from the 
"top") as computations push more results on the belt. As I understand 
it, the HW implementation is indeed like a renaming/forwarding network, 
although the "names" (offsets from the "top") are known to the compiler 
because of the static instruction sheduling and known latencies of all 
operations.

> What I meant by "stack" is the place where scratch registers and
> in-flight belt values get pushed/popped when you enter/leave a function,
> which give you a kind of "register window" functionality. 

Ah, apologies for my wrong assumption. (But calling that a "stack" risks 
confusion with the normal SW stack in memory, which is certainly still 
needed in a Mill processor, for example to pass function arguments by 
reference.)

I agree that the Mill architecture, with its "new belt for each call" 
and "new scratch-pad for each call" programmer's model, is similar to 
register-window designs.

> IIRC the Mill
> documents it as living in memory but the moment when stack elements
> actually reach memory was never clearly specified, so I assume the
> idea was that it could be kept in "second class registers" (IIRC
> that was managed by the "spiller" you refer to).

As I understood it, the HW implementation of the Mill's 
function-specific belt and function-specific scratch-pad is not meant to 
be visible to a normal application program running in a Mill processor. 
A function executing in a normal program cannot access the belt of its 
caller, nor the scratch-pad of its caller.

For debuggers and other system tools that need such visiblity the intent 
was to provide a dedicated (HW-dependent) interface or "service", 
essentially an interface to the spiller HW. But the structure of the 
spiller and its buffers and memory areas is not part of the visible Mill 
architecture, rather it is specific to each implementation ("model") of 
a Mill processor core.

> Of course, in a traditional CPU, the top of the stack is kept in the L1
> cache and only ever touches the higher levels of the memory hierarchy
> when cache pressure is very high or upon context switches, so the L1
> cache plays a similar role.

A similar role from the performance point of view, yes, with the 
difference that data in the L1 cache is accessed via normal load/store 
instructions, while the spiller data structures would not be accessible 
in that way.

As I understood it, the spiller would have some private internal buffers 
for your "stack", and would use main memory (via the caches) as backup 
when the private buffers overflowed. Thus the most recently spilled data 
would be either in the spiller's private buffers or in the L1 cache.

> Not sure if a set of "second class
> registers" dedicated to storing the top of the stack (like SPARC has,
> and the Mill seemed to want to have) can be made to be faster and/or
> lower power than the L1 cache to justify the effort.

I am not a HW guy, but I think the answer is yes. However, speed is not 
the only advanage of such "second class" registers: they can also make 
for a simpler programmer's model where the second-class registers are 
hidden, implicit, and need not (and perhaps cannot) be named in the 
instructions.

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