Re: Register windows

From	Stefan Monnier <monnier@iro.umontreal.ca>
Newsgroups	comp.arch
Subject	Re: Register windows
Date	2025-07-18 11:29 -0400
Organization	A noiseless patient Spider
Message-ID	<jwvfretfs4u.fsf-monnier+comp.arch@gnu.org> (permalink)
References	(16 earlier) <1059t3a$16euf$1@dont-email.me> <1059tti$16il5$1@dont-email.me> <f19813b55e635188c81f989aa63f0462@www.novabbs.org> <jwvldomkdua.fsf-monnier+comp.arch@gnu.org> <mdv6hmFheagU1@mid.individual.net>

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> The Mill "belt" (I assume this is what you call the "stack") corresponds to
> the "first-class registers": all computations take operands from the belt
> and push results to the belt. When a function is called, it sees a fresh
> belt with only its "in" arguments; when the function returns, it leaves its
> "out" results pushed on the belt that the caller sees.

That's right.  The belt is the closest that the Mill has to "first-class
registers", tho in a sense it addresses elements of the forwarding
network more than "registers".

What I meant by "stack" is the place where scratch registers and
in-flight belt values get pushed/popped when you enter/leave a function,
which give you a kind of "register window" functionality.  IIRC the Mill
documents it as living in memory but the moment when stack elements
actually reach memory was never clearly specified, so I assume the
idea was that it could be kept in "second class registers" (IIRC
that was managed by the "spiller" you refer to).

Of course, in a traditional CPU, the top of the stack is kept in the L1
cache and only ever touches the higher levels of the memory hierarchy
when cache pressure is very high or upon context switches, so the L1
cache plays a similar role.  Not sure if a set of "second class
registers" dedicated to storing the top of the stack (like SPARC has,
and the Mill seemed to want to have) can be made to be faster and/or
lower power than the L1 cache to justify the effort.


        Stefan

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