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Groups > sci.electronics.design > #740194
| From | Bill Sloman <bill.sloman@ieee.org> |
|---|---|
| Newsgroups | sci.electronics.design |
| Subject | Re: AI Will Create More Jobs Than It Eliminates By 2027 |
| Date | 2026-02-07 15:44 +1100 |
| Organization | A noiseless patient Spider |
| Message-ID | <10m6fvb$ooav$4@dont-email.me> (permalink) |
| References | (8 earlier) <ufg9okd1aoaq4560cv2p0r2qu12nfa74kd@4ax.com> <10m43b8$3si94$8@dont-email.me> <g8lbokh5shoq22sc9djcmrnaa96ohpp8gf@4ax.com> <10m4rgh$68rj$4@dont-email.me> <vs6cok9qmkgoli0ssqjcu0hsfvftptpaq6@4ax.com> |
On 7/02/2026 4:06 am, john larkin wrote: > On Sat, 7 Feb 2026 00:48:50 +1100, Bill Sloman <bill.sloman@ieee.org> > wrote: > >> On 6/02/2026 10:56 pm, john larkin wrote: >>> On Fri, 6 Feb 2026 17:56:26 +1100, Bill Sloman <bill.sloman@ieee.org> >>> wrote: >>> >>>> On 6/02/2026 3:29 am, john larkin wrote: >>>>> On Thu, 5 Feb 2026 16:01:29 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>> wrote: >>>>> >>>>>> On 5/02/2026 3:33 am, john larkin wrote: >>>>>>> On Wed, 4 Feb 2026 23:50:25 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>> wrote: >>>>>>> >>>>>>>> On 4/02/2026 10:37 pm, john larkin wrote: >>>>>>>>> On Wed, 4 Feb 2026 16:39:39 +1100, Bill Sloman <bill.sloman@ieee.org> >>>>>>>>> wrote: >>>>>>>>> >>>>>>>>>> On 4/02/2026 3:24 am, john larkin wrote: >>>>>>>>>>> On Tue, 03 Feb 2026 08:03:02 -0800, Jeff Liebermann <jeffl@cruzio.com> >>>>>>>>>>> wrote: >>>>>>>>>>> >>>>>>>>>>>> On Mon, 02 Feb 2026 20:47:06 -0800, john larkin <jl@glen--canyon.com> >>>>>>>>>>>> wrote: >>>>>>>>>>>> >>>>>>>>>>>>> On Mon, 02 Feb 2026 19:37:43 -0800, Jeff Liebermann <jeffl@cruzio.com> >>>>>>>>>>>>> wrote: >>>>>>>>>>>>> >>>>>>>>>>>>>> On Mon, 02 Feb 2026 17:29:26 -0800, john larkin <jl@glen--canyon.com> >>>>>>>>>>>>>> wrote: >>>>>>>>>>>>>> >>>>>>>>>>>>>>> On Mon, 02 Feb 2026 14:33:15 -0800, Jeff Liebermann <jeffl@cruzio.com> >>>>>>>>>>>>>>> wrote: >>>>>>>>>>>>>>> >>>>>>>>>>>>>>>> On Mon, 02 Feb 2026 10:05:09 -0800, john larkin <jl@glen--canyon.com> >>>>>>>>>>>>>>>> wrote: >>>>>>>> >>>>>>>> <snip> >>>>>>>> >>>>>>>>> We can buy cheap surface-mount XOs with ps or even fs of RMS jitter. >>>>>>>>> It's the DDS part that wrecks things. For 50 cents it looks like we >>>>>>>>> can generate any frequency up to 40 MHz with ps jitter and 36-bit >>>>>>>>> frequency resolution. It's cool to play with. >>>>>>>> >>>>>>>> You don't have to let the logic gates inside your FPGA wreck the jitter >>>>>>>> - the noise on the power rails inside the FPGA can do that - but if you >>>>>>>> use ECLinpS D-type clocked by your crystal oscillator to resynchronise >>>>>>>> the output of the FPGA to the edges of of your crystal clock you can get >>>>>>>> rid of a lot of that. You do have to be a bit careful to pick up FPGA >>>>>>>> output at a time when it is guaranteed stable - I generated a four phase >>>>>>>> version of the clock when I did it, and selected the phase with the best >>>>>>>> phase margin at final test to create the cleaned up output, but that was >>>>>>>> for a retrofitted clean-up. >>>>>>> >>>>>>> Our XO is 25 MHz. We use a PLL inside the FPGA to multiply that to 250 >>>>>>> MHz, which clocks the DDS phase accumulator and some other logic. >>>>>>> That's free. >>>>>> >>>>>> But nasty. Back in 1995 I could buy a 500HMHz crystal controlled >>>>>> oscillator with a 1 psec jitter spec. It wasn't all that cheap. >>>>>> >>>>>> There are parts that rely on surface acoustic waves that run even >>>>>> faster.They weren't off the shelf parts back then, so I wasn't interested. >>>>>> >>>>>>>>> https://www.dropbox.com/scl/fi/n12quxajp59egahv1b48i/DDS_1KHz.jpg?rlkey=8w0tlr3h1rxeif3byepzub947&raw=1 >>>>>>>>> >>>>>>>>> There's a tiny non-monoticity step at the zero crossing, caused by the >>>>>>>>> resistance of the FPGA outputs. That can be tuned out. >>>>>>>> >>>>>>>> Resistance alone will only generate a lag. Non-mononicity implies >>>>>>>> ringing - the output resistance isn't high enough to damp the inductive >>>>>>>> elements, but more resistance should tune that out. >>>>>>> >>>>>>> The resistance of the MSB pin output makes the step size wrong and >>>>>>> makes the sine wave zero cross non-monotonic. >>>>>>> >>>>>>> https://www.dropbox.com/scl/fi/exwm68xr6uwya4jyu2cbc/X116_DDS.jpg?rlkey=3b72xlxwi73uk22ni9cs80fix&raw=1 >>>>>> >>>>>> That's a remarkably cheap and nasty ADC. Buffer the FPGA outputs with >>>>>> proper switches and even you should be able to do a lot better. >>>>> >>>>> It's not a nasty ADC. It's a pretty good 6-bit DAC. >>>>> >>>>>> >>>>>>> Changing the 250r resistor to 238 makes it look nice. In frequency >>>>>>> domain, I guess the mismatch creates a spike at the MSB frequency >>>>>>> that's hard to filter and makes jitter. I think. >>>>>> >>>>>> Sometimes it pays to split the MSB over two switches so the >>>>>> non-linearity of the switch resistance is less salient. >>>>> >>>>> That would work. We're paralleling two pins somewhere else. But just >>>>> changing the MSB resisttor works too. I can't experiment with >>>>> paralleling because the FPGA is a BGA. >>>>> >>>>> My guys picked some FPFA pins for the MSBs that don't have >>>>> programmable drive strength, otherwise we could play with that. >>>>> >>>>> >>>>>> >>>>>>> We'll synth an octave of frequency and not ever run at 1 KHz, but >>>>>>> running slow lets us see the waveform steps. >>>>>> >>>>>> But not clearly enough to let you see how to improve them. >>>>> >>>>> I just found a small monoticity problem and fixed it. Maybe I'll FFT >>>>> the 1KHz sine wave and play with that too. Just for fun: the clock >>>>> generator looks great already. >>>>> >>>>>> >>>>>>> Scoping the bits gets amazing as we get anywhere near Nyquist. One >>>>>>> could swear they are all random noise, but they sum into a beautiful >>>>>>> sine. Building your own DDS is worth it for the amusement alone. >>>>>>> >>>>>>>> >>>>>>>> ECLinPS is designed to drive transmission lines, so it shouldn't exhibit >>>>>>>> that particular problem. >>>>>>> >>>>>>> One eclips gate costs about as much as our FPGA. And 15x as much as >>>>>>> our CPU. >>>>>>> >>>>>>> The T20 is using about 30 mA of core current, about 40 milliwatts, to >>>>>>> run a lot of stuff, including the 250 MHz DDS. Imagine the power and >>>>>>> cost of a bunch of ECL flops. And how would you make the ECLs into the >>>>>>> sine wave? Use an ECL-input DAC? >>>>>> >>>>>> You don't have to imagine the power and cost of a bunch of ECLinPs >>>>>> D-type monostables. They have part numbers and data sheets. >>>>> >>>>> My apologies for suggesting that you might ever have any imagination. >>>> >>>> Your ideas about what imagination looks like and how it works are a bit >>>> comical. Sensible people don't use their imaginations to find out >>>> documented facts. >>>> >>>>>> https://www.onsemi.com/download/data-sheet/pdf/mc10ep451-d.pdf >>>>>> >>>>>> Digikey seems to stock the MC100EP451. >>>>>> >>>>>> https://www.digikey.com/en/products/filter/logic/flip-flops/706?s=N4IgTCBcDaILIGECMAGFBRACgFgKxJAF0BfIA >>>>>> >>>>>> The cheapest unit price is $US 10.39 and the typical current drain is >>>>>> listed as 95mA. >>>>>> >>>>>> An ECL-input DAC would work, but you could use something quite as cheap >>>>>> and nasty as your current improvised DAC, but hanging of the ECL outputs. >>>>>> >>>>>> What your revelations have made clear is that your problems with your >>>>>> sinewave output aren't due to any kind of timing problem, but rather >>>>>> your choice of a particularly cheap and nasty improvised DAC. >>>>> >>>>> I don't have problems. I have a great DDS clock source for under 50 >>>>> cents. >>>> Sure you do. You want to describe a cheap and nasty version of a DDS >>>> clock source as "great". The word would be "adequate" if you haven't >>>> missed any other problems it may have. >>>> >>>>> It can be reprogrammed for frequency in nanoseconds, unlike >>>>> commercial expensive DDS chips with klunky interfaces. >>>> >>>> Most of them are intended to be used with an analog filter on the output >>>> and that filter will have a settling time longer than nanoseconds. >>> >>> I'm using a very simple 50 MHz lowpass filter. That settles in under >>> 10 ns. >>> >>> An Analog Devices DDS typically has a very pokey SPI interface and >>> costs around $15. >>> >>> Not many people make DDS chips these days. Maybe just ADI. >> >> It's easy to make them in FPGAs. >> >>> I ran an FFT on my sine wave at 10 KHz. The filter has no effect that >>> low. I'm seeing a 2nd harmonic about 20 dB down. Not terrible. >> >> Considering how crappy your improvised DAC is, 20dB is surprisingly good. >> >> A better DAC should do quite a bit better. > > It would be big and expensive. My "dac" costs about 5 cents. It would more expensive. "Big" is pretty unspecific. There are some small relatively cheap fast DACs around - or there were when I last looked. >> Second harmonic distortion is entirely the top half of your sine wave >> being different from the bottom half. Tuning the most significant bit of >> your DAC output could probably reduce it dramatically. > > Given a 250 MHz clock, risetime/falltime asymmetry could explain some > of the -20 spike. What I have so far is plenty good... well under 1 ns > p-p jitter on my Rigol scope. Granting that your FPGA gates have a finite and probably output voltage dependent output impedance, the the second harmonic distortion is almost certainly coming from that. The rise-time/fall-time asymmetry had much less effect than that last time I looked at it. > I'll probably wait until it's on the final-product PCB to fine-tune > it. I'll have a different lowpass filter and a comparator right there, > not the fuzzy sine wave on a 50 ohm scope. > > This DDS thing had endless opportunities for tweaking. My FPGA guy did > a 12-bit (4096 entry) sine lookup table with 6 bits out. I suppose one > could cancel the 2nd harmonic by distorting the lookup table a bit. If the FPGA production process is stable, and produces identical gate output resistances from part to part. > > This could be a student project for someone. Only if you dislike them intensely. > I thought that making a 50-cent DDS was a cool idea. You obviously > don't. It's not exactly original, or recent. -- Bill Sloman, Sydney
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AI Will Create More Jobs Than It Eliminates By 2027 Don Y <blockedofcourse@foo.invalid> - 2026-02-02 04:38 -0700
Re: AI Will Create More Jobs Than It Eliminates By 2027 john larkin <jl@glen--canyon.com> - 2026-02-02 07:37 -0800
Re: AI Will Create More Jobs Than It Eliminates By 2027 Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> - 2026-02-02 11:37 -0500
Re: AI Will Create More Jobs Than It Eliminates By 2027 john larkin <jl@glen--canyon.com> - 2026-02-02 08:57 -0800
Re: AI Will Create More Jobs Than It Eliminates By 2027 john larkin <jl@glen--canyon.com> - 2026-02-03 15:15 -0800
Re: AI Will Create More Jobs Than It Eliminates By 2027 Bill Sloman <bill.sloman@ieee.org> - 2026-02-05 00:59 +1100
Re: AI Will Create More Jobs Than It Eliminates By 2027 john larkin <jl@glen--canyon.com> - 2026-02-04 08:52 -0800
Re: AI Will Create More Jobs Than It Eliminates By 2027 Bill Sloman <bill.sloman@ieee.org> - 2026-02-05 16:37 +1100
Re: AI Will Create More Jobs Than It Eliminates By 2027 john larkin <jl@glen--canyon.com> - 2026-02-05 08:13 -0800
Re: AI Will Create More Jobs Than It Eliminates By 2027 Bill Sloman <bill.sloman@ieee.org> - 2026-02-06 17:43 +1100
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Re: AI Will Create More Jobs Than It Eliminates By 2027 Don Y <blockedofcourse@foo.invalid> - 2026-02-02 12:07 -0700
Re: AI Will Create More Jobs Than It Eliminates By 2027 Jeff Liebermann <jeffl@cruzio.com> - 2026-02-02 14:33 -0800
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