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| From | Gerhard Hoffmann <dk4xp@arcor.de> |
|---|---|
| Newsgroups | sci.electronics.design |
| Subject | Re: AI Will Create More Jobs Than It Eliminates By 2027 |
| Date | 2026-02-05 12:38 +0100 |
| Message-ID | <10m1vfs$aclp$1@solani.org> (permalink) |
| References | (8 earlier) <10lum32$233h2$1@dont-email.me> <i9b6ok5hds7c6ski9nan3l7e1agbmhemml@4ax.com> <10lvfao$2ater$1@dont-email.me> <o9s6oktffesgvrj9rrglqg58vamfclptb8@4ax.com> <10m187t$2ufvl$1@dont-email.me> |
Am 05.02.26 um 06:01 schrieb Bill Sloman:
>> Our XO is 25 MHz. We use a PLL inside the FPGA to multiply that to 250
>> MHz, which clocks the DDS phase accumulator and some other logic.
>> That's free.
In an ideal world, that costs 20 dB of phase noise for the f*10.
The real world is usually worse.
I think the ECOC2522 100 MHz oven is at quite a good price/
performance ratio
<
https://www.digikey.de/de/products/detail/ecs-inc/ECOC-2522-100-000-3FC/6578492
>
From a 2*LVC125 driver you get quite a lot of energy at 300 MHz,
just filter it. At 5V5 even more.
< https://www.flickr.com/photos/137684711@N07/51331765527/in/datetaken/ >
Any ideas for 300 MHz SAW filters that are not unobtainium??
400 MHz is easy.
Just the right clock for my LMX2595 synthesizer.
< https://www.ti.com/lit/ds/symlink/lmx2595.pdf >
You can operate an array of these synthesizers with the same
settings and the phase noise averages out. The price of the
chip sets a natural limit on averaging, however.
> But nasty. Back in 1995 I could buy a 500HMHz crystal controlled
> oscillator with a 1 psec jitter spec. It wasn't all that cheap.
>
> There are parts that rely on surface acoustic waves that run even
> faster.They weren't off the shelf parts back then, so I wasn't interested.
>
You can get whispering gallery mode sapphire oscs as a catalog item
from Poseidon Scientific in .au at 10 GHz or so.
Size of a shoe box and the price hurts.
In Idar-Oberstein, a town 30 km from here, is the German Gem Museum.
When my then lil daughter was still in her princess age, we were often
there and watched the pretty rocks. I then meditated what interesting
things could be done with one of these huge saphire blocks, when I had
the grinding & the cooling problem solved.
Factoid: Idar-Oberstein must be the most American town possible, Bruce
Willis was born there.
More on timing etc, a bonanza:
< https://rubiola.org/ >
<
https://rubiola.org/pdf-lectures/Scient-Instrum-Files/Phase%20noise%20Wiley%2C%20Ch2%20updated%20draft.pdf
>
< https://rubiola.org/pdf-articles/journal/2011-TUFFC--Elisa.pdf >
>>>> https://www.dropbox.com/scl/fi/n12quxajp59egahv1b48i/DDS_1KHz.jpg?
>>>> rlkey=8w0tlr3h1rxeif3byepzub947&raw=1
>>>>
>>>> There's a tiny non-monoticity step at the zero crossing, caused by the
>>>> resistance of the FPGA outputs. That can be tuned out.
The real problem is that the effective point of the zero crossing
jitters by up to 1 clock with 1 LSB amplitude unless you generate
an exact subharmonic of the clock. And then it comes from a chip
dissipating maybe a Watt on completely unpredictable frequencies
and the ground bounce accompanies it.
> You don't have to imagine the power and cost of a bunch of ECLinPs D-
> type monostables. They have part numbers and data sheets.
In Crawford's Frequency synthesizer Design Handbook is a plot
that compares ECL, TTL, FACT etc with regard to phase noise.
ACT wins hands down. The book predates LVC.
Gerhard
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