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Re: AI for FPGA design

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From Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De>
Newsgroups sci.electronics.design, comp.arch.fpga
Subject Re: AI for FPGA design
Date Mon, 11 Aug 2025 11:25:31 +0200
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Cross-posted to 2 groups.

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On Mon, 11 Aug 2025, Bill Sloman wrote:
"On 11/08/2025 6:32 am, john larkin wrote:
[. . .]
> 
> Then why produce Verilog code?

True. Programmers should write everything in hex code, rather than using the
crutch of assembler or some even higher level language."


Dear Mister Sloman,

I believe that what Mister Larkin is getting at here, is that he wants to 
use an AI at a higher level than Verilog, so Mister Larkin is perplexed as 
to why Ben Cohen advocates an electronics worker to both use Perplexity AI 
to produce Verilog code and to continue manually writing in Verilog.

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Thread

AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-09 07:09 -0700
  Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-10 21:20 +0200
    Re: AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-10 13:32 -0700
      Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 01:06 +0200
      Re: AI for FPGA design Bill Sloman <bill.sloman@ieee.org> - 2025-08-11 13:58 +1000
        Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 11:25 +0200
          Re: AI for FPGA design Bill Sloman <bill.sloman@ieee.org> - 2025-08-12 16:32 +1000
          Re: AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-12 07:51 -0700
    Re: AI for FPGA design "Edward Rawde" <invalid@invalid.invalid> - 2025-08-11 00:36 -0400
      Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 11:17 +0200
    Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 12:29 +0200
  Re: AI for FPGA design legalize+jeeves@mail.xmission.com (Richard) - 2025-08-11 16:57 +0000

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