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AI for FPGA design

From john larkin <jl@glen--canyon.com>
Newsgroups sci.electronics.design, comp.arch.fpga
Subject AI for FPGA design
Date 2025-08-09 07:09 -0700
Organization A noiseless patient Spider
Message-ID <64le9k1vou92tug582k53qhfijm118r68k@4ax.com> (permalink)

Cross-posted to 2 groups.

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It seems to be happening, according to AI.

It would be cool to design FPGAs at a higher level than VHDL or
Verilog. 

https://www.campusreform.org/article/gen-z-right-facing-big-problem-no-previous-generation-encountered/28270

Recent grads are complaining that they can't find jobs because of AI.
One estimate I've seen (from an EE student) is that 95% of EE grads
are coders, not circuit designers. So far, AI doesn't seem to be very
good at analog circuit design.

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AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-09 07:09 -0700
  Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-10 21:20 +0200
    Re: AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-10 13:32 -0700
      Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 01:06 +0200
      Re: AI for FPGA design Bill Sloman <bill.sloman@ieee.org> - 2025-08-11 13:58 +1000
        Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 11:25 +0200
          Re: AI for FPGA design Bill Sloman <bill.sloman@ieee.org> - 2025-08-12 16:32 +1000
          Re: AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-12 07:51 -0700
    Re: AI for FPGA design "Edward Rawde" <invalid@invalid.invalid> - 2025-08-11 00:36 -0400
      Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 11:17 +0200
    Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 12:29 +0200
  Re: AI for FPGA design legalize+jeeves@mail.xmission.com (Richard) - 2025-08-11 16:57 +0000

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