Groups | Search | Server Info | Login | Register

Groups > comp.arch.fpga > #38652

Re: AI for FPGA design

Cross-posted to 2 groups.

Show all headers | View raw

On Sun, 10 Aug 2025 21:20:33 +0200, Niocláisín Cóilín de Ghlostéir
<Spamassassin@irrt.De> wrote:

>Dear Mister Larkin:
>
>Ben Cohen posts many LinkedIn posts via which he promotes Perplexity AI 
>for helps with Verilog - not to avoid Verilog.
>
>A lady claims via LinkedIn that an AI service produced a bad Verilog code, 
>so she concluded that an AI is not going to threaten her job, and I wrote 
>to her that she deserves a refund.

Then why produce Verilog code?

Back to comp.arch.fpga | Previous | Next — Previous in thread | Next in thread | Find similar

Thread

AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-09 07:09 -0700
  Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-10 21:20 +0200
    Re: AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-10 13:32 -0700
      Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 01:06 +0200
      Re: AI for FPGA design Bill Sloman <bill.sloman@ieee.org> - 2025-08-11 13:58 +1000
        Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 11:25 +0200
          Re: AI for FPGA design Bill Sloman <bill.sloman@ieee.org> - 2025-08-12 16:32 +1000
          Re: AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-12 07:51 -0700
    Re: AI for FPGA design "Edward Rawde" <invalid@invalid.invalid> - 2025-08-11 00:36 -0400
      Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 11:17 +0200
    Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 12:29 +0200
  Re: AI for FPGA design legalize+jeeves@mail.xmission.com (Richard) - 2025-08-11 16:57 +0000

csiph-web