Re: AI for FPGA design

From	Bill Sloman <bill.sloman@ieee.org>
Newsgroups	sci.electronics.design, comp.arch.fpga
Subject	Re: AI for FPGA design
Date	2025-08-11 13:58 +1000
Organization	A noiseless patient Spider
Message-ID	<107bpou$2aa9j$1@dont-email.me> (permalink)
References	<64le9k1vou92tug582k53qhfijm118r68k@4ax.com> <ff700ae7-08a7-bf40-f29a-69c44bd31ae7@irrt.De> <hd0i9kdsmqu8eb2k2vht0j55bd5ipgvn8h@4ax.com>

Cross-posted to 2 groups.

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On 11/08/2025 6:32 am, john larkin wrote:
> On Sun, 10 Aug 2025 21:20:33 +0200, Niocláisín Cóilín de Ghlostéir
> <Spamassassin@irrt.De> wrote:
> 
>> Dear Mister Larkin:
>>
>> Ben Cohen posts many LinkedIn posts via which he promotes Perplexity AI
>> for helps with Verilog - not to avoid Verilog.
>>
>> A lady claims via LinkedIn that an AI service produced a bad Verilog code,
>> so she concluded that an AI is not going to threaten her job, and I wrote
>> to her that she deserves a refund.
> 
> Then why produce Verilog code?

True. Programmers should write everything in hex code, rather than using 
the crutch of assembler or some even higher level language.

It wouldn't help their productivity, and it would make it even harder 
for the people maintaining the product to work out which segment of code 
or chunk of logic was actually doing what, but at least you know what's 
actually going on, even if you can't work out what it was intended to be 
doing, or why.

-- 
Bill Sloman, Sydney

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AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-09 07:09 -0700
  Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-10 21:20 +0200
    Re: AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-10 13:32 -0700
      Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 01:06 +0200
      Re: AI for FPGA design Bill Sloman <bill.sloman@ieee.org> - 2025-08-11 13:58 +1000
        Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 11:25 +0200
          Re: AI for FPGA design Bill Sloman <bill.sloman@ieee.org> - 2025-08-12 16:32 +1000
          Re: AI for FPGA design john larkin <jl@glen--canyon.com> - 2025-08-12 07:51 -0700
    Re: AI for FPGA design "Edward Rawde" <invalid@invalid.invalid> - 2025-08-11 00:36 -0400
      Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 11:17 +0200
    Re: AI for FPGA design Niocláisín Cóilín de Ghlostéir <Spamassassin@irrt.De> - 2025-08-11 12:29 +0200
  Re: AI for FPGA design legalize+jeeves@mail.xmission.com (Richard) - 2025-08-11 16:57 +0000

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