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[tip:x86/process] x86/msr: Rename MISC_FEATURE_ENABLES to MISC_FEATURES_ENABLES

From tip-bot for Kyle Huey <tipbot@zytor.com>
Newsgroups linux.kernel
Subject [tip:x86/process] x86/msr: Rename MISC_FEATURE_ENABLES to MISC_FEATURES_ENABLES
Date 2017-03-20 17:40 +0100
Message-ID <tn8vF-7pZ-53@gated-at.bofh.it> (permalink)
References <tn0HL-1Xo-7@gated-at.bofh.it>
Organization linux.* mail to news gateway

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Commit-ID:  ab6d9468631a6e56e4c071c6ce6710956485fe08
Gitweb:     http://git.kernel.org/tip/ab6d9468631a6e56e4c071c6ce6710956485fe08
Author:     Kyle Huey <me@kylehuey.com>
AuthorDate: Mon, 20 Mar 2017 01:16:19 -0700
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Mon, 20 Mar 2017 16:10:32 +0100

x86/msr: Rename MISC_FEATURE_ENABLES to MISC_FEATURES_ENABLES

This matches the only public Intel documentation of this MSR, in the
"Virtualization Technology FlexMigration Application Note"
(preserved at https://bugzilla.kernel.org/attachment.cgi?id=243991)

Signed-off-by: Kyle Huey <khuey@kylehuey.com>
Cc: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Cc: kvm@vger.kernel.org
Cc: Radim Krčmář <rkrcmar@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andi Kleen <andi@firstfloor.org>
Cc: linux-kselftest@vger.kernel.org
Cc: Nadav Amit <nadav.amit@gmail.com>
Cc: Robert O'Callahan <robert@ocallahan.org>
Cc: Richard Weinberger <richard@nod.at>
Cc: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Len Brown <len.brown@intel.com>
Cc: Shuah Khan <shuah@kernel.org>
Cc: user-mode-linux-devel@lists.sourceforge.net
Cc: Jeff Dike <jdike@addtoit.com>
Cc: Alexander Viro <viro@zeniv.linux.org.uk>
Cc: user-mode-linux-user@lists.sourceforge.net
Cc: David Matlack <dmatlack@google.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Dmitry Safonov <dsafonov@virtuozzo.com>
Cc: linux-fsdevel@vger.kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>
Link: http://lkml.kernel.org/r/20170320081628.18952-2-khuey@kylehuey.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

---
 arch/x86/include/asm/msr-index.h | 6 +++---
 arch/x86/kernel/cpu/intel.c      | 8 ++++----
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4c928f3..f429b70 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -553,10 +553,10 @@
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT	39
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
 
-/* MISC_FEATURE_ENABLES non-architectural features */
-#define MSR_MISC_FEATURE_ENABLES	0x00000140
+/* MISC_FEATURES_ENABLES non-architectural features */
+#define MSR_MISC_FEATURES_ENABLES	0x00000140
 
-#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT		1
+#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT	1
 
 #define MSR_IA32_TSC_DEADLINE		0x000006E0
 
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 0631977..e229318 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -91,13 +91,13 @@ static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
 	}
 
 	if (ring3mwait_disabled) {
-		msr_clear_bit(MSR_MISC_FEATURE_ENABLES,
-			      MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
+		msr_clear_bit(MSR_MISC_FEATURES_ENABLES,
+			      MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
 		return;
 	}
 
-	msr_set_bit(MSR_MISC_FEATURE_ENABLES,
-		    MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
+	msr_set_bit(MSR_MISC_FEATURES_ENABLES,
+		    MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
 
 	set_cpu_cap(c, X86_FEATURE_RING3MWAIT);

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Thread

[PATCH v16 0/10] x86/arch_prctl Add ARCH_[GET|SET]_CPUID for controlling the CPUID instruction Kyle Huey <me@kylehuey.com> - 2017-03-20 09:20 +0100
  [PATCH v16 01/10] x86/msr: Rename MISC_FEATURE_ENABLES to MISC_FEATURES_ENABLES Kyle Huey <me@kylehuey.com> - 2017-03-20 09:20 +0100
    [tip:x86/process] x86/msr: Rename MISC_FEATURE_ENABLES to  MISC_FEATURES_ENABLES tip-bot for Kyle Huey <tipbot@zytor.com> - 2017-03-20 17:40 +0100
  [PATCH v16 10/10] KVM: x86: virtualize cpuid faulting Kyle Huey <me@kylehuey.com> - 2017-03-20 09:40 +0100
  [PATCH v16 09/10] x86/arch_prctl: Selftest for ARCH_[GET|SET]_CPUID Kyle Huey <me@kylehuey.com> - 2017-03-20 16:50 +0100
  Re: [PATCH v16 08/10] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Thomas Gleixner <tglx@linutronix.de> - 2017-03-20 17:20 +0100
    Re: [PATCH v16 08/10] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Kyle Huey <me@kylehuey.com> - 2017-03-20 18:00 +0100
  [PATCH v16 04/10] x86/arch_prctl/64: Rename do_arch_prctl to do_arch_prctl_64 Kyle Huey <me@kylehuey.com> - 2017-03-20 17:50 +0100
  [PATCH v16 08/10] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID Kyle Huey <me@kylehuey.com> - 2017-03-20 17:50 +0100
  [PATCH v16 02/10] x86/arch_prctl: Rename 'code' argument to 'option' Kyle Huey <me@kylehuey.com> - 2017-03-20 17:50 +0100
  [PATCH v16 05/10] x86/arch_prctl: Add do_arch_prctl_common Kyle Huey <me@kylehuey.com> - 2017-03-20 17:50 +0100
  [PATCH v16 07/10] x86/cpufeature: Detect CPUID faulting support Kyle Huey <me@kylehuey.com> - 2017-03-20 17:50 +0100
  [PATCH v16 03/10] x86/arch_prctl/64: Use SYSCALL_DEFINE2 to define sys_arch_prctl Kyle Huey <me@kylehuey.com> - 2017-03-20 18:00 +0100
  [PATCH v16 06/10] x86/syscalls/32: Wire up arch_prctl on x86-32 Kyle Huey <me@kylehuey.com> - 2017-03-20 18:00 +0100

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