Re: [PATCH] brcmnand: Fix up the flash cache register offset for older controllers

From	Florian Fainelli <f.fainelli@gmail.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH] brcmnand: Fix up the flash cache register offset for older controllers
Date	2017-07-05 20:20 +0200
Message-ID	<tZX46-1jQ-9@gated-at.bofh.it> (permalink)
References	<tZWB4-Ve-23@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On 07/05/2017 10:46 AM, Karl Beldan wrote:
> From: Karl Beldan <karl.beldan-ext@sagemcom.com>
> 
> Tested on BCM{63138,6838,63268} and cross checked with the various
> *_map_part.h which the brcmnand_regs_v* in brcmnand.c have historically
> been derived from.

BCM63138 is using a 7.0 controller, 6838 uses a 5.0 controller, but has
a separate flash cache register which does indeed end up at 0x400 bytes
off the main FLASH block, and finally 63268 does have a v4.0 controller
and the flash cache is also in a separate register that makes it end up
at 0x400.

Your change, as proposed would break chips like 7425 which use 5.0
controller with the flash cache at 0x200 bytes.

The binding describes an optional flash-cache register cell that you can
specify, so that's probably what you want to do here?

> 
> Cc: Brian Norris <computersforpeace@gmail.com>
> Cc: Kamal Dasu <kdasu.kdev@gmail.com>
> Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
> Cc: Richard Weinberger <richard@nod.at>
> Cc: David Woodhouse <dwmw2@infradead.org>
> Cc: Marek Vasut <marek.vasut@gmail.com>
> Cc: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
> Signed-off-by: Karl Beldan <karl.beldan-ext@sagemcom.com>
> ---
>  drivers/mtd/nand/brcmnand/brcmnand.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/brcmnand/brcmnand.c b/drivers/mtd/nand/brcmnand/brcmnand.c
> index 7419c5c..e6371ff6 100644
> --- a/drivers/mtd/nand/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/brcmnand/brcmnand.c
> @@ -250,7 +250,7 @@ static const u16 brcmnand_regs_v40[] = {
>  	[BRCMNAND_OOB_READ_10_BASE]	= 0x130,
>  	[BRCMNAND_OOB_WRITE_BASE]	=  0x30,
>  	[BRCMNAND_OOB_WRITE_10_BASE]	=     0,
> -	[BRCMNAND_FC_BASE]		= 0x200,
> +	[BRCMNAND_FC_BASE]		= 0x400,
>  };
>  
>  /* BRCMNAND v5.0 */
> @@ -280,7 +280,7 @@ static const u16 brcmnand_regs_v50[] = {
>  	[BRCMNAND_OOB_READ_10_BASE]	= 0x130,
>  	[BRCMNAND_OOB_WRITE_BASE]	=  0x30,
>  	[BRCMNAND_OOB_WRITE_10_BASE]	= 0x140,
> -	[BRCMNAND_FC_BASE]		= 0x200,
> +	[BRCMNAND_FC_BASE]		= 0x400,
>  };
>  
>  /* BRCMNAND v6.0 - v7.1 */
> 


-- 
Florian

Thread

[PATCH] brcmnand: Fix up the flash cache register offset for older controllers Karl Beldan <karl.beldan@gmail.com> - 2017-07-05 19:50 +0200
  Re: [PATCH] brcmnand: Fix up the flash cache register offset for  older controllers Florian Fainelli <f.fainelli@gmail.com> - 2017-07-05 20:20 +0200
    Re: [PATCH] brcmnand: Fix up the flash cache register offset for  older controllers Brian Norris <computersforpeace@gmail.com> - 2017-07-05 20:20 +0200
    Re: [PATCH] brcmnand: Fix up the flash cache register offset for  older controllers Karl Beldan <karl.beldan@gmail.com> - 2017-07-05 23:00 +0200

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