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Groups > linux.kernel > #1481016

[PATCH 05/15] x86/mce/AMD: Read MSRs on the CPU allocating the threshold blocks

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From: Yazen Ghannam <Yazen.Ghannam@amd.com>

Scalable MCA systems allow non-core MCA banks to only be accessible by
certain CPUs. The MSRs for these banks are Read-as-Zero on other CPUs.

During allocate_threshold_blocks(), get_block_address() can be scheduled
on CPUs other than the one allocating the block. This causes the MSRs to
be read on the wrong CPU and results in incorrect behavior.

Add a @cpu parameter to get_block_address() and pass this in to ensure
that the MSRs are only read on the CPU that is allocating the block.

Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1472673994-12235-2-git-send-email-Yazen.Ghannam@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 17 ++++++++---------
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 419e0ee3b12f..9da92fb2e073 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -293,7 +293,7 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 	wrmsr(MSR_CU_DEF_ERR, low, high);
 }
 
-static u32 get_block_address(u32 current_addr, u32 low, u32 high,
+static u32 get_block_address(unsigned int cpu, u32 current_addr, u32 low, u32 high,
 			     unsigned int bank, unsigned int block)
 {
 	u32 addr = 0, offset = 0;
@@ -309,13 +309,13 @@ static u32 get_block_address(u32 current_addr, u32 low, u32 high,
 			 */
 			u32 low, high;
 
-			if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
+			if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
 				return addr;
 
 			if (!(low & MCI_CONFIG_MCAX))
 				return addr;
 
-			if (!rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
+			if (!rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high) &&
 			    (low & MASK_BLKPTR_LO))
 				addr = MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
 		}
@@ -421,12 +421,12 @@ out:
 void mce_amd_feature_init(struct cpuinfo_x86 *c)
 {
 	u32 low = 0, high = 0, address = 0;
-	unsigned int bank, block;
+	unsigned int bank, block, cpu = smp_processor_id();
 	int offset = -1;
 
 	for (bank = 0; bank < mca_cfg.banks; ++bank) {
 		for (block = 0; block < NR_BLOCKS; ++block) {
-			address = get_block_address(address, low, high, bank, block);
+			address = get_block_address(cpu, address, low, high, bank, block);
 			if (!address)
 				break;
 
@@ -544,15 +544,14 @@ static void amd_deferred_error_interrupt(void)
 static void amd_threshold_interrupt(void)
 {
 	u32 low = 0, high = 0, address = 0;
-	int cpu = smp_processor_id();
-	unsigned int bank, block;
+	unsigned int bank, block, cpu = smp_processor_id();
 
 	/* assume first bank caused it */
 	for (bank = 0; bank < mca_cfg.banks; ++bank) {
 		if (!(per_cpu(bank_map, cpu) & (1 << bank)))
 			continue;
 		for (block = 0; block < NR_BLOCKS; ++block) {
-			address = get_block_address(address, low, high, bank, block);
+			address = get_block_address(cpu, address, low, high, bank, block);
 			if (!address)
 				break;
 
@@ -774,7 +773,7 @@ static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
 	if (err)
 		goto out_free;
 recurse:
-	address = get_block_address(address, low, high, bank, ++block);
+	address = get_block_address(cpu, address, low, high, bank, ++block);
 	if (!address)
 		return 0;
 
-- 
2.10.0

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Thread

[PATCH 00/15] x86/RAS queue for 4.9 Borislav Petkov <bp@alien8.de> - 2016-09-12 10:00 +0200
  [PATCH 13/15] x86/mce/AMD: Extract the error address on SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 15/15] x86/RAS/mce_amd_inj: Fix some W= warnings Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
    [tip:ras/core] x86/RAS/mce_amd_inj: Fix some W= warnings tip-bot for Borislav Petkov <tipbot@zytor.com> - 2016-09-13 15:40 +0200
  [PATCH 04/15] x86/RAS: Add syndrome support to mce_amd_inj Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 09/15] x86/mce/AMD: Update sysfs bank names for SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 07/15] EDAC/mce_amd: Use SMCA prefix for error descriptions arrays Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 10/15] x86/mce/AMD: Ensure the deferred error interrupt is of type APIC on SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 01/15] x86/mce/AMD: Use msr_ops.misc() in allocate_threshold_blocks() Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 06/15] EDAC/mce_amd: Add missing SMCA error descriptions Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 11/15] x86/mce/AMD: Save MCA_IPID in MCE struct on SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 03/15] EDAC/mce_amd: Print syndrome register value on SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 14/15] x86/MCE/AMD, EDAC: Handle reserved bank 4 on Fam17h properly Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 12/15] x86/mce, EDAC/mce_amd: Print MCA_SYND and MCA_IPID during MCE on SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 05/15] x86/mce/AMD: Read MSRs on the CPU allocating the threshold blocks Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 02/15] x86/mce: Add support for new MCA_SYND register Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 08/15] x86/mce/AMD, EDAC/mce_amd: Define and use tables for known SMCA IP types Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200

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