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Groups > linux.kernel > #1481006

[PATCH 09/15] x86/mce/AMD: Update sysfs bank names for SMCA systems

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From: Yazen Ghannam <Yazen.Ghannam@amd.com>

Define a bank's sysfs filename based on its IP type and InstanceId.

Aravind:
* General idea and proto- get_name().
* Define smca_umc_block_names[] and buf_mcatype[].

Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1473193490-3291-2-git-send-email-Yazen.Ghannam@amd.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 49 ++++++++++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 3b74b62d0808..0f9d0786bc97 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 #include <linux/cpu.h>
 #include <linux/smp.h>
+#include <linux/string.h>
 
 #include <asm/amd_nb.h>
 #include <asm/apic.h>
@@ -63,6 +64,11 @@ static const char * const th_names[] = {
 	"execution_unit",
 };
 
+static const char * const smca_umc_block_names[] = {
+	"dram_ecc",
+	"misc_umc"
+};
+
 struct smca_bank_name smca_bank_names[] = {
 	[SMCA_LS]	= { "load_store",	"Load Store Unit" },
 	[SMCA_IF]	= { "insn_fetch",	"Instruction Fetch Unit" },
@@ -113,6 +119,17 @@ static struct smca_hwid_mcatype smca_hwid_mcatypes[] = {
 struct smca_bank_info smca_banks[MAX_NR_BANKS];
 EXPORT_SYMBOL_GPL(smca_banks);
 
+/*
+ * In SMCA enabled processors, we can have multiple banks for a given IP type.
+ * So to define a unique name for each bank, we use a temp c-string to append
+ * the MCA_IPID[InstanceId] to type's name in get_name().
+ *
+ * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
+ * is greater than 8 plus 1 (for underscore) plus length of longest type name.
+ */
+#define MAX_MCATYPE_NAME_LEN	30
+static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
+
 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
 static DEFINE_PER_CPU(unsigned int, bank_map);	/* see which banks are on */
 
@@ -769,6 +786,34 @@ static struct kobj_type threshold_ktype = {
 	.default_attrs		= default_attrs,
 };
 
+static const char *get_name(unsigned int bank, struct threshold_block *b)
+{
+	unsigned int bank_type;
+
+	if (!mce_flags.smca) {
+		if (b && bank == 4)
+			return bank4_names(b);
+
+		return th_names[bank];
+	}
+
+	if (!smca_banks[bank].type)
+		return NULL;
+
+	bank_type = smca_banks[bank].type->bank_type;
+
+	if (b && bank_type == SMCA_UMC) {
+		if (b->block < ARRAY_SIZE(smca_umc_block_names))
+			return smca_umc_block_names[b->block];
+		return NULL;
+	}
+
+	snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
+		 "%s_%x", smca_bank_names[bank_type].name,
+			  smca_banks[bank].type_instance);
+	return buf_mcatype;
+}
+
 static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
 				     unsigned int block, u32 address)
 {
@@ -823,7 +868,7 @@ static int allocate_threshold_blocks(unsigned int cpu, unsigned int bank,
 
 	err = kobject_init_and_add(&b->kobj, &threshold_ktype,
 				   per_cpu(threshold_banks, cpu)[bank]->kobj,
-				   (bank == 4 ? bank4_names(b) : th_names[bank]));
+				   get_name(bank, b));
 	if (err)
 		goto out_free;
 recurse:
@@ -878,7 +923,7 @@ static int threshold_create_bank(unsigned int cpu, unsigned int bank)
 	struct device *dev = per_cpu(mce_device, cpu);
 	struct amd_northbridge *nb = NULL;
 	struct threshold_bank *b = NULL;
-	const char *name = th_names[bank];
+	const char *name = get_name(bank, NULL);
 	int err = 0;
 
 	if (is_shared_bank(bank)) {
-- 
2.10.0

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[PATCH 00/15] x86/RAS queue for 4.9 Borislav Petkov <bp@alien8.de> - 2016-09-12 10:00 +0200
  [PATCH 13/15] x86/mce/AMD: Extract the error address on SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 15/15] x86/RAS/mce_amd_inj: Fix some W= warnings Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
    [tip:ras/core] x86/RAS/mce_amd_inj: Fix some W= warnings tip-bot for Borislav Petkov <tipbot@zytor.com> - 2016-09-13 15:40 +0200
  [PATCH 04/15] x86/RAS: Add syndrome support to mce_amd_inj Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 09/15] x86/mce/AMD: Update sysfs bank names for SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 07/15] EDAC/mce_amd: Use SMCA prefix for error descriptions arrays Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 10/15] x86/mce/AMD: Ensure the deferred error interrupt is of type APIC on SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 01/15] x86/mce/AMD: Use msr_ops.misc() in allocate_threshold_blocks() Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 06/15] EDAC/mce_amd: Add missing SMCA error descriptions Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 11/15] x86/mce/AMD: Save MCA_IPID in MCE struct on SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 03/15] EDAC/mce_amd: Print syndrome register value on SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 14/15] x86/MCE/AMD, EDAC: Handle reserved bank 4 on Fam17h properly Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 12/15] x86/mce, EDAC/mce_amd: Print MCA_SYND and MCA_IPID during MCE on SMCA systems Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 05/15] x86/mce/AMD: Read MSRs on the CPU allocating the threshold blocks Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 02/15] x86/mce: Add support for new MCA_SYND register Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200
  [PATCH 08/15] x86/mce/AMD, EDAC/mce_amd: Define and use tables for known SMCA IP types Borislav Petkov <bp@alien8.de> - 2016-09-12 10:10 +0200

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