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Re: [RFC, PATCHv1 00/28] 5-level paging

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On Friday, December 9, 2016 6:01:30 AM CET Ingo Molnar wrote:
> >   - Handle opt-in wider address space for userspace.
> > 
> >     Not all userspace is ready to handle addresses wider than current
> >     47-bits. At least some JIT compiler make use of upper bits to encode
> >     their info.
> > 
> >     We need to have an interface to opt-in wider addresses from userspace
> >     to avoid regressions.
> > 
> >     For now, I've included testing-only patch which bumps TASK_SIZE to
> >     56-bits. This can be handy for testing to see what breaks if we max-out
> >     size of virtual address space.
> 
> So this is just a detail - but it sounds a bit limiting to me to provide an 'opt 
> in' flag for something that will work just fine on the vast majority of 64-bit 
> software.
> 
> Please make this an opt out compatibility flag instead: similar to how we handle 
> address space layout limitations/quirks ABI details, such as ADDR_LIMIT_32BIT, 
> ADDR_LIMIT_3GB, ADDR_COMPAT_LAYOUT, READ_IMPLIES_EXEC, etc.

We've had a similar discussion about JIT software on ARM64, which has a wide
range of supported page table layouts and some software wants to limit that
to a specific number.

I don't remember the outcome of that discussion, but I'm adding a few people
to Cc that might remember.

There have also been some discussions in the past to make the depth of the
page table a per-task decision on s390, since you may have some tasks that
run just fine with two or three levels of paging while another task actually
wants the full 64-bit address space. I wonder how much extra work this would
be on top of the boot-time option.

	Arnd

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[RFC, PATCHv1 00/28] 5-level paging "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
  [RFC, PATCHv1 24/28] x86/mm: add sync_global_pgds() for configuration with 5-level paging "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
    Re: [RFC, PATCHv1 24/28] x86/mm: add sync_global_pgds() for  configuration with 5-level paging Andy Lutomirski <luto@amacapital.net> - 2016-12-08 19:50 +0100
      Re: [RFC, PATCHv1 24/28] x86/mm: add sync_global_pgds() for  configuration with 5-level paging "Kirill A. Shutemov" <kirill@shutemov.name> - 2016-12-08 20:40 +0100
  [RFC, PATCHv1 19/28] x86/mm: basic defines/helpers for CONFIG_X86_5LEVEL "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
  [RFC, PATCHv1 04/28] asm-generic: introduce <asm-generic/pgtable-nop4d.h> "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
  [RFC, PATCHv1 17/28] x86/mm: define virtual memory map for 5-level paging "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
    Re: [RFC, PATCHv1 17/28] x86/mm: define virtual memory map for  5-level paging Randy Dunlap <rdunlap@infradead.org> - 2016-12-08 20:00 +0100
      Re: [RFC, PATCHv1 17/28] x86/mm: define virtual memory map for  5-level paging "Kirill A. Shutemov" <kirill@shutemov.name> - 2016-12-08 20:30 +0100
  [RFC, PATCHv1 27/28] x86: enable la57 support "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
  [QEMU, PATCH] x86: implement la57 paging mode "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
    Re: [Qemu-devel] [QEMU, PATCH] x86: implement la57 paging mode no-reply@patchew.org - 2016-12-08 17:50 +0100
  [RFC, PATCHv1 28/28] TESTING-ONLY: bump TASK_SIZE_MAX "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
  [RFC, PATCHv1 03/28] arch, mm: convert all architectures to use 5level-fixup.h "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
  [RFC, PATCHv1 18/28] x86/paravirt: make paravirt code support 5-level paging "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
  [RFC, PATCHv1 07/28] x86: trivial portion of 5-level paging conversion "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
  [RFC, PATCHv1 01/28] asm-generic: introduce 5level-fixup.h "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
  [RFC, PATCHv1 26/28] x86/mm: add support for 5-level paging for KASLR "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:30 +0100
  [RFC, PATCHv1 06/28] x86: basic changes into headers for 5-level paging "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:40 +0100
  [RFC, PATCHv1 02/28] asm-generic: introduce __ARCH_USE_5LEVEL_HACK "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> - 2016-12-08 17:40 +0100
  Re: [RFC, PATCHv1 00/28] 5-level paging Linus Torvalds <torvalds@linux-foundation.org> - 2016-12-08 19:20 +0100
    Re: [RFC, PATCHv1 00/28] 5-level paging hpa@zytor.com - 2016-12-08 19:30 +0100
    Re: [RFC, PATCHv1 00/28] 5-level paging "Kirill A. Shutemov" <kirill@shutemov.name> - 2016-12-08 20:30 +0100
  Re: [RFC, PATCHv1 00/28] 5-level paging Ingo Molnar <mingo@kernel.org> - 2016-12-09 06:10 +0100
    Re: [RFC, PATCHv1 00/28] 5-level paging Arnd Bergmann <arnd@arndb.de> - 2016-12-09 11:30 +0100
      Re: [RFC, PATCHv1 00/28] 5-level paging Catalin Marinas <catalin.marinas@arm.com> - 2016-12-09 12:00 +0100
    Re: [RFC, PATCHv1 00/28] 5-level paging "Kirill A. Shutemov" <kirill@shutemov.name> - 2016-12-09 11:40 +0100
      Re: [RFC, PATCHv1 00/28] 5-level paging Andi Kleen <ak@linux.intel.com> - 2016-12-09 17:50 +0100
        Re: [RFC, PATCHv1 00/28] 5-level paging "Kirill A. Shutemov" <kirill@shutemov.name> - 2016-12-09 18:30 +0100
      Re: [RFC, PATCHv1 00/28] 5-level paging Dave Hansen <dave.hansen@intel.com> - 2016-12-09 17:50 +0100

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