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Groups > linux.kernel > #1516217
| From | Gabriel Fernandez <gabriel.fernandez@st.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 2/6] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board |
| Date | 2016-11-07 15:10 +0100 |
| Message-ID | <sASMy-4aH-7@gated-at.bofh.it> (permalink) |
| References | <sARQt-3wK-5@gated-at.bofh.it> <sARQt-3wK-13@gated-at.bofh.it> <sASCX-3R8-31@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Hi Daniel,
On 11/07/2016 02:55 PM, Daniel Thompson wrote:
> On 07/11/16 13:05, gabriel.fernandez@st.com wrote:
>> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>>
>> In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or
>> from pll-sai-p.
>>
>> The SDIO clock could be also derived from 48Mhz or from sys clock.
>>
>> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
>> ---
>> drivers/clk/clk-stm32f4.c | 18 +++++++++++++++++-
>> 1 file changed, 17 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
>> index 7641acd..dda15bc 100644
>> --- a/drivers/clk/clk-stm32f4.c
>> +++ b/drivers/clk/clk-stm32f4.c
>> @@ -199,7 +199,7 @@ struct stm32f4_gate_data {
>> { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
>> { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
>> { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
>> - { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
>> + { STM32F4_RCC_APB2ENR, 11, "sdio", "sdmux" },
>
> I'm confused. How do the "sdmux" clock come to exist on STM32F429?
>
"sdmux" only exist on STM32F469 (struct stm32f4_gate_data stm32f469_gates[])
BR
Gabriel
>
>> { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
>> { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
>> { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
>> @@ -940,6 +940,10 @@ static struct clk_hw *stm32_register_cclk(struct
>> device *dev, const char *name,
>> "no-clock", "lse", "lsi", "hse-rtc"
>> };
>>
>> +static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
>> +
>> +static const char *sdmux_parents[2] = { "pll48", "sys" };
>> +
>> struct stm32f4_clk_data {
>> const struct stm32f4_gate_data *gates_data;
>> const u64 *gates_map;
>> @@ -1109,6 +1113,18 @@ static void __init stm32f4_rcc_init(struct
>> device_node *np)
>> goto fail;
>> }
>>
>> + if (of_device_is_compatible(np, "st,stm32f469-rcc")) {
>> + clk_hw_register_mux_table(NULL, "pll48",
>> + pll48_parents, ARRAY_SIZE(pll48_parents), 0,
>> + base + STM32F4_RCC_DCKCFGR, 27, 1, 0, NULL,
>> + &stm32f4_clk_lock);
>> +
>> + clk_hw_register_mux_table(NULL, "sdmux",
>> + sdmux_parents, ARRAY_SIZE(sdmux_parents), 0,
>> + base + STM32F4_RCC_DCKCFGR, 28, 1, 0, NULL,
>> + &stm32f4_clk_lock);
>> + }
>> +
>> of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
>> return;
>> fail:
>>
>
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[PATCH 0/6] Add STM32F4 missing clocks <gabriel.fernandez@st.com> - 2016-11-07 14:10 +0100
[PATCH 2/6] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board <gabriel.fernandez@st.com> - 2016-11-07 14:10 +0100
Re: [PATCH 2/6] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board Daniel Thompson <daniel.thompson@linaro.org> - 2016-11-07 15:00 +0100
Re: [PATCH 2/6] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-07 15:10 +0100
[PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock <gabriel.fernandez@st.com> - 2016-11-07 14:10 +0100
Re: [PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock Daniel Thompson <daniel.thompson@linaro.org> - 2016-11-07 15:00 +0100
Re: [PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-07 15:20 +0100
[PATCH 4/6] clk: stm32f4: Add I2S clock <gabriel.fernandez@st.com> - 2016-11-07 14:10 +0100
Re: [PATCH 4/6] clk: stm32f4: Add I2S clock Daniel Thompson <daniel.thompson@linaro.org> - 2016-11-07 15:20 +0100
Re: [PATCH 4/6] clk: stm32f4: Add I2S clock Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-08 17:30 +0100
[PATCH 6/6] arm: dts: stm32f4: Add external I2S clock <gabriel.fernandez@st.com> - 2016-11-07 14:20 +0100
[PATCH 5/6] clk: stm32f4: Add SAI clocks <gabriel.fernandez@st.com> - 2016-11-07 14:20 +0100
[PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards <gabriel.fernandez@st.com> - 2016-11-07 14:20 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-07 15:10 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Radosław Pietrzyk <radoslaw.pietrzyk@gmail.com> - 2016-11-07 16:00 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-08 09:40 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Radosław Pietrzyk <radoslaw.pietrzyk@gmail.com> - 2016-11-08 10:00 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-08 17:30 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Radosław Pietrzyk <radoslaw.pietrzyk@gmail.com> - 2016-11-09 09:20 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-09 11:00 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Daniel Thompson <daniel.thompson@linaro.org> - 2016-11-07 18:50 +0100
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