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Groups > linux.kernel > #1516209
| From | Daniel Thompson <daniel.thompson@linaro.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock |
| Date | 2016-11-07 15:00 +0100 |
| Message-ID | <sASCW-3R8-9@gated-at.bofh.it> (permalink) |
| References | <sARQt-3wK-5@gated-at.bofh.it> <sARQu-3wK-27@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 07/11/16 13:05, gabriel.fernandez@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@st.com>
>
> This patch adds post dividers of I2S & SAI PLLs.
> These dividers are managed by a dedicated register (RCC_DCKCFGR).
> The PLL should be off before a set rate.
> This patch also introduces the lcd-tft clock.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
> drivers/clk/clk-stm32f4.c | 27 +++++++++++++++++++++++++--
> 1 file changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
> index dda15bc..5fa5d51 100644
> --- a/drivers/clk/clk-stm32f4.c
> +++ b/drivers/clk/clk-stm32f4.c
> @@ -215,6 +215,7 @@ struct stm32f4_gate_data {
> enum {
> SYSTICK, FCLK, CLK_LSI, CLK_LSE, CLK_HSE_RTC, CLK_RTC,
> PLL_VCO_I2S, PLL_VCO_SAI,
> + CLK_LCD,
> END_PRIMARY_CLK
> };
>
> @@ -599,6 +600,9 @@ static struct clk_hw *clk_register_pll_div(const char *name,
> static const struct clk_div_table pll_divp_table[] = {
> { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 },
> };
> +static const struct clk_div_table pll_lcd_div_table[] = {
> + { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 },
> +};
>
> /*
> * Decode current PLL state and (statically) model the state we inherit from
> @@ -659,16 +663,35 @@ static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
> clk_register_pll_div(data->p_name, data->vco_name, 0, reg,
> 16, 2, 0, pll_divp_table, pll_hw, lock);
>
> - if (data->q_name)
> + if (data->q_name) {
> clk_register_pll_div(data->q_name, data->vco_name, 0, reg,
> 24, 4, CLK_DIVIDER_ONE_BASED, NULL,
> pll_hw, lock);
>
> - if (data->r_name)
> + if (data->pll_num == PLL_I2S)
> + clk_register_pll_div("plli2s-q-div", data->q_name,
> + 0, base + STM32F4_RCC_DCKCFGR,
> + 0, 5, 0, NULL, pll_hw, &stm32f4_clk_lock);
> +
> + if (data->pll_num == PLL_SAI)
> + clk_register_pll_div("pllsai-q-div", data->q_name,
> + 0, base + STM32F4_RCC_DCKCFGR,
> + 8, 5, 0, NULL, pll_hw, &stm32f4_clk_lock);
> + }
Shouldn't this be in the config structures?
It seems very odd to me to allow the config structures to control
whether we take the branch or not and then add these hard coded hacks.
Daniel.
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[PATCH 0/6] Add STM32F4 missing clocks <gabriel.fernandez@st.com> - 2016-11-07 14:10 +0100
[PATCH 2/6] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board <gabriel.fernandez@st.com> - 2016-11-07 14:10 +0100
Re: [PATCH 2/6] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board Daniel Thompson <daniel.thompson@linaro.org> - 2016-11-07 15:00 +0100
Re: [PATCH 2/6] clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-07 15:10 +0100
[PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock <gabriel.fernandez@st.com> - 2016-11-07 14:10 +0100
Re: [PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock Daniel Thompson <daniel.thompson@linaro.org> - 2016-11-07 15:00 +0100
Re: [PATCH 3/6] clk: stm32f4: Add post divisor for I2S & SAI PLLs and Add lcd-tft clock Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-07 15:20 +0100
[PATCH 4/6] clk: stm32f4: Add I2S clock <gabriel.fernandez@st.com> - 2016-11-07 14:10 +0100
Re: [PATCH 4/6] clk: stm32f4: Add I2S clock Daniel Thompson <daniel.thompson@linaro.org> - 2016-11-07 15:20 +0100
Re: [PATCH 4/6] clk: stm32f4: Add I2S clock Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-08 17:30 +0100
[PATCH 6/6] arm: dts: stm32f4: Add external I2S clock <gabriel.fernandez@st.com> - 2016-11-07 14:20 +0100
[PATCH 5/6] clk: stm32f4: Add SAI clocks <gabriel.fernandez@st.com> - 2016-11-07 14:20 +0100
[PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards <gabriel.fernandez@st.com> - 2016-11-07 14:20 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-07 15:10 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Radosław Pietrzyk <radoslaw.pietrzyk@gmail.com> - 2016-11-07 16:00 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-08 09:40 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Radosław Pietrzyk <radoslaw.pietrzyk@gmail.com> - 2016-11-08 10:00 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-08 17:30 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Radosław Pietrzyk <radoslaw.pietrzyk@gmail.com> - 2016-11-09 09:20 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Gabriel Fernandez <gabriel.fernandez@st.com> - 2016-11-09 11:00 +0100
Re: [PATCH 1/6] clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards Daniel Thompson <daniel.thompson@linaro.org> - 2016-11-07 18:50 +0100
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