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Groups > linux.kernel > #1342286
| From | Vikas Shivappa <vikas.shivappa@intel.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH 2/5] x86/mbm: Intel Memory B/W Monitoring enumeration and init |
| Date | 2016-02-24 19:20 +0100 |
| Message-ID | <r5Mcy-8nW-3@gated-at.bofh.it> (permalink) |
| References | <r0NVE-1Am-7@gated-at.bofh.it> <r0O5k-1E8-9@gated-at.bofh.it> <r5ERJ-36A-43@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Wed, 24 Feb 2016, Thomas Gleixner wrote:
> On Wed, 10 Feb 2016, Vikas Shivappa wrote:ar
>> +static int intel_mbm_init(void)
>> +{
>> + int ret = 0, array_size, maxid = cqm_max_rmid + 1;
>> +
>> + mbm_socket_max = cpumask_weight(&cqm_cpumask);
>
> This should use the new topology_max_packages() function, so you can alloc
> your array correctly even if not all sockets are online/plugged yet.
Will fix. Thanks for pointing out.
>
>> + array_size = sizeof(struct sample) * maxid * mbm_socket_max;
>> + mbm_local = kmalloc(array_size, GFP_KERNEL);
>> + if (!mbm_local) {
>> + ret = -ENOMEM;
>
> return -ENOMEM is sufficient here.
Will fix
>
>> + goto out;
>> + }
>> +
>> + mbm_total = kmalloc(array_size, GFP_KERNEL);
>> + if (!mbm_total) {
>> + kfree(mbm_local);
>> + ret = -ENOMEM;
>> + }
>> +out:
>> +
>> + return ret;
>> +}
>> +
>> cqm_l3_scale = boot_cpu_data.x86_cache_occ_scale;
>> @@ -1384,14 +1520,34 @@ static int __init intel_cqm_init(void)
>>
>> __perf_cpu_notifier(intel_cqm_cpu_notifier);
>
> You really should register the notifier _AFTER_ registering the pmu. That
> needs to be fixed anyway, because the existing code leaks the notifier AND
> memory in case perf_pmu_register fails.
Correct, Will fix the notifier leak
Thanks,
Vikas
>
> Thanks,
>
> tglx
>
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Re: [PATCH 2/5] x86/mbm: Intel Memory B/W Monitoring enumeration and init Thomas Gleixner <tglx@linutronix.de> - 2016-02-24 11:30 +0100
Re: [PATCH 2/5] x86/mbm: Intel Memory B/W Monitoring enumeration and init Vikas Shivappa <vikas.shivappa@intel.com> - 2016-02-24 19:20 +0100
Re: [PATCH 2/5] x86/mbm: Intel Memory B/W Monitoring enumeration and init Thomas Gleixner <tglx@linutronix.de> - 2016-02-24 20:30 +0100
Re: [PATCH 2/5] x86/mbm: Intel Memory B/W Monitoring enumeration and init Vikas Shivappa <vikas.shivappa@intel.com> - 2016-02-24 21:10 +0100
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