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Re: What cache-archtectures ...

From "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com>
Newsgroups comp.lang.c++
Subject Re: What cache-archtectures ...
Date 2019-12-20 14:04 -0800
Organization Aioe.org NNTP Server
Message-ID <qtjgic$1mbc$1@gioia.aioe.org> (permalink)
References <qtdfc2$p96$1@news.albasani.net> <qtjdtd$ef7$3@dont-email.me>

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On 12/20/2019 1:20 PM, Vir Campestris wrote:
> On 18/12/2019 15:07, Bonita Montero wrote:
>> .... could make std::hardware_destructive_interference_size
>> and std::hardware_constructive_interference_size different?
> 
> Multi-level caches perhaps?
> 

Yeah. Was thinking that std::hardware_destructive_interference_size can 
be L1, and std::hardware_constructive_interference_size different can be 
L2. However, this is completely up to the implementation.

Iirc, back on early hyperthreading 128-byte would be split into two 
64-byte halves. Iirc, two adjacent 64-bit cache lines can interfere.

https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf

They recommend to pad and align things on 128-byte boundaries. The two 
64-byte halves can contend. Section 3.7.3, Hardware Prefetching for 
Second-Level Cache.

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Thread

What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-18 16:07 +0100
  Re: What cache-archtectures ... Vir Campestris <vir.campestris@invalid.invalid> - 2019-12-20 21:20 +0000
    Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-20 14:04 -0800
      Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-21 08:18 +0100
        Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-22 17:24 -0800
          Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-22 17:35 -0800
          Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-24 13:18 +0100
            Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-24 13:39 -0800
            Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-24 13:41 -0800
              Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-25 02:30 +0100
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:52 -0800
                Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-28 08:54 +0100
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:57 -0800
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-27 23:59 -0800
                Re: What cache-archtectures ... Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-28 09:53 +0100
                Re: What cache-archtectures ... "Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> - 2019-12-28 15:56 -0800

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