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Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS

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>>> The syscon block is a general subsystem control block, and it is not
>>> specifically only for controlling reset and enabling clocks (other
>>> functions include serdes control, for example). It is also shared
>>> with other peripherals.
>>>
>>> So we can remove the ctrl-reg property (since it is not part of the
>>> SAS controller), and add the relevant syscon register offsets to the
>>> "hisilicon,sas-syscon" property, like this:
>>> hisilicon,sas-syscon = <&sas_ctrl0 0xa60 0x33c 0x5a30 0xa64 0x338>;
>>>
>>> Ok?
>>
>> It would be better to have each offset in a separate property.
>>
> These register are not used for different purpose.
> Instead, they are all used for one purpose, reset the sas controller;
> Though a bit complicated, the silicon has special requirement here.
>
> So still prefer using the original method,
> ctrl-reg = <0xa60 0x33c 0x5a30 0xa64 0x338>;
> Since we can simply use of_property_read_u32_array.
>
We can actually remove the deassert and clock enable properties as they 
are always at a fixed offset from their respective assert/clk disable 
partner register.

> Thanks
>
>
> .
>

thanks,
John

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[PATCH v2 00/32] HiSilicon SAS driver John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
  [PATCH v2 16/32] scsi: hisi_sas: add timer and spinlock init John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
  [PATCH v2 09/32] scsi: hisi_sas: add slot init code John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
  [PATCH v2 10/32] scsi: hisi_sas: add cq structure initialization John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
  [PATCH v2 18/32] scsi: hisi_sas: add v1 hardware register definitions John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
  [PATCH v2 05/32] scsi: hisi_sas: scan device tree John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
    Re: [PATCH v2 05/32] scsi: hisi_sas: scan device tree Mark Rutland <mark.rutland@arm.com> - 2015-10-26 15:50 +0100
      Re: [PATCH v2 05/32] scsi: hisi_sas: scan device tree John Garry <john.garry@huawei.com> - 2015-10-26 16:00 +0100
  [PATCH v2 13/32] scsi: hisi_sas: add hisi_hba workqueue John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 19/32] scsi: hisi_sas: add v1 HW initialisation code John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 07/32] scsi: hisi_sas: allocate memories and create pools John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 12/32] scsi: hisi_sas: set dev DMA mask John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
    Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS Mark Rutland <mark.rutland@arm.com> - 2015-10-26 15:50 +0100
      Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS John Garry <john.garry@huawei.com> - 2015-10-27 14:20 +0100
        Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS Mark Rutland <mark.rutland@arm.com> - 2015-10-27 15:40 +0100
          Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS zhangfei <zhangfei.gao@linaro.org> - 2015-10-27 16:00 +0100
            Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS Mark Rutland <mark.rutland@arm.com> - 2015-10-27 16:10 +0100
            Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS John Garry <john.garry@huawei.com> - 2015-10-27 16:10 +0100
    Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS John Garry <john.garry@huawei.com> - 2015-10-26 16:10 +0100
  [PATCH v2 04/32] scsi: hisi_sas: add scsi host registration John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 11/32] scsi: hisi_sas: add phy SAS ADDR initialization John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 20/32] scsi: hisi_sas: add v1 hw interrupt init John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 17/32] scsi: hisi_sas: add v1 hw module init John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100

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