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Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS

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On 26/10/2015 14:45, Mark Rutland wrote:
> On Mon, Oct 26, 2015 at 10:14:33PM +0800, John Garry wrote:
>> Add devicetree bindings for HiSilicon SAS driver.
>>
>> Signed-off-by: John Garry <john.garry@huawei.com>
>> ---
>>   .../devicetree/bindings/scsi/hisilicon-sas.txt     | 70 ++++++++++++++++++++++
>>   1 file changed, 70 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>>
>> diff --git a/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>> new file mode 100644
>> index 0000000..d1e7b2a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
>> @@ -0,0 +1,70 @@
>> +* HiSilicon SAS controller
>> +
>> +The HiSilicon SAS controller supports SAS/SATA.
>> +
>> +Main node required properties:
>> +  - compatible : value should be as follows:
>> +	(a) "hisilicon,sas-controller-v1" for v1 of HiSilicon SAS controller IP
>> +  - reg : Address and length of the SAS register
>> +  - hisilicon,sas-syscon: phandle of syscon used for sas control
>> +  - ctrl-reg : offset to the following SAS control registers (in order):
>> +		- reset assert
>> +		- clock disable
>> +		- reset status
>> +		- reset de-assert
>> +		- clock enable
>
> This needs a better name, and it should probably be split up into
> several properties.
>
> However, it sounds like the syscon is actually a clock+reset
> controller, and should be modelled as such. It's not actually a part of
> the SAS controller as such.

The syscon block is a general subsystem control block, and it is not 
specifically only for controlling reset and enabling clocks (other 
functions include serdes control, for example). It is also shared with 
other peripherals.

So we can remove the ctrl-reg property (since it is not part of the SAS 
controller), and add the relevant syscon register offsets to the 
"hisilicon,sas-syscon" property, like this:
hisilicon,sas-syscon = <&sas_ctrl0 0xa60 0x33c 0x5a30 0xa64 0x338>;

Ok?

>
>> +  - queue-count : number of delivery and completion queues in the controller
>> +  - phy-count : number of phys accessible by the controller
>> +  - interrupts : Interrupts for phys, completion queues, and fatal
>> +		 interrupts:
>> +		  - Each phy has 3 interrupt sources:
>> +			- broadcast
>> +			- phyup
>> +			- abnormal
>> +		  - Each completion queue has 1 interrupt source
>> +		  - Each controller has 2 fatal interrupt sources:
>> +			- ECC
>> +			- AXI bus
>
> Please make the ordering explicit here (you might only need to add the
> phrase "in order" in a few places).

Will do.

>
> Thanks,
> Mark.
>
Thanks,
John


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[PATCH v2 00/32] HiSilicon SAS driver John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
  [PATCH v2 16/32] scsi: hisi_sas: add timer and spinlock init John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
  [PATCH v2 09/32] scsi: hisi_sas: add slot init code John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
  [PATCH v2 10/32] scsi: hisi_sas: add cq structure initialization John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
  [PATCH v2 18/32] scsi: hisi_sas: add v1 hardware register definitions John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
  [PATCH v2 05/32] scsi: hisi_sas: scan device tree John Garry <john.garry@huawei.com> - 2015-10-26 15:10 +0100
    Re: [PATCH v2 05/32] scsi: hisi_sas: scan device tree Mark Rutland <mark.rutland@arm.com> - 2015-10-26 15:50 +0100
      Re: [PATCH v2 05/32] scsi: hisi_sas: scan device tree John Garry <john.garry@huawei.com> - 2015-10-26 16:00 +0100
  [PATCH v2 13/32] scsi: hisi_sas: add hisi_hba workqueue John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 19/32] scsi: hisi_sas: add v1 HW initialisation code John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 07/32] scsi: hisi_sas: allocate memories and create pools John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 12/32] scsi: hisi_sas: set dev DMA mask John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
    Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS Mark Rutland <mark.rutland@arm.com> - 2015-10-26 15:50 +0100
      Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS John Garry <john.garry@huawei.com> - 2015-10-27 14:20 +0100
        Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS Mark Rutland <mark.rutland@arm.com> - 2015-10-27 15:40 +0100
          Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS zhangfei <zhangfei.gao@linaro.org> - 2015-10-27 16:00 +0100
            Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS Mark Rutland <mark.rutland@arm.com> - 2015-10-27 16:10 +0100
            Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS John Garry <john.garry@huawei.com> - 2015-10-27 16:10 +0100
    Re: [PATCH v2 02/32] devicetree: bindings: scsi: HiSi SAS John Garry <john.garry@huawei.com> - 2015-10-26 16:10 +0100
  [PATCH v2 04/32] scsi: hisi_sas: add scsi host registration John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 11/32] scsi: hisi_sas: add phy SAS ADDR initialization John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 20/32] scsi: hisi_sas: add v1 hw interrupt init John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100
  [PATCH v2 17/32] scsi: hisi_sas: add v1 hw module init John Garry <john.garry@huawei.com> - 2015-10-26 15:20 +0100

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