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Groups > linux.kernel > #1303532
| From | Xing Zheng <zhengxing@rock-chips.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH v2 2/5] clk: rockchip: rk3036: fix uarts clock error |
| Date | 2016-01-07 13:20 +0100 |
| Message-ID | <qOhHR-7YB-33@gated-at.bofh.it> (permalink) |
| References | <qOhHP-7YB-1@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Due to a copy-paste error the uart1 and uart2 clock div set
incorrect, we should to fix it.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 7e3b41c..04b5249 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -242,11 +242,11 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
RK2928_CLKGATE_CON(1), 8, GFLAGS),
COMPOSITE_NOMUX(0, "uart1_src", "uart_pll_clk", 0,
- RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
- RK2928_CLKGATE_CON(1), 8, GFLAGS),
+ RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(1), 10, GFLAGS),
COMPOSITE_NOMUX(0, "uart2_src", "uart_pll_clk", 0,
- RK2928_CLKSEL_CON(13), 0, 7, DFLAGS,
- RK2928_CLKGATE_CON(1), 8, GFLAGS),
+ RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
+ RK2928_CLKGATE_CON(1), 12, GFLAGS),
COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
RK2928_CLKSEL_CON(17), 0,
RK2928_CLKGATE_CON(1), 9, GFLAGS,
--
1.7.9.5
--
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[PATCH v2 0/5] fix some clock configuration for the RK3036 platform Xing Zheng <zhengxing@rock-chips.com> - 2016-01-07 13:20 +0100
[PATCH v2 3/5] clk: rockchip: rk3036: fix the div offset for emac clock Xing Zheng <zhengxing@rock-chips.com> - 2016-01-07 13:20 +0100
[PATCH v2 2/5] clk: rockchip: rk3036: fix uarts clock error Xing Zheng <zhengxing@rock-chips.com> - 2016-01-07 13:20 +0100
[PATCH v2 1/5] clk: rockchip: rk3036: fix the FLAGs for clock mux Xing Zheng <zhengxing@rock-chips.com> - 2016-01-07 13:20 +0100
[PATCH v2 4/5] clk: rockchip: rk3036: rename emac ext source clock Xing Zheng <zhengxing@rock-chips.com> - 2016-01-07 13:20 +0100
[PATCH v2 5/5] clk: rockchip: rk3036: add HCLK_MAC id for emac Xing Zheng <zhengxing@rock-chips.com> - 2016-01-07 13:30 +0100
Re: [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Heiko Stuebner <heiko@sntech.de> - 2016-01-09 21:40 +0100
Re: [PATCH v2 0/5] fix some clock configuration for the RK3036 platform Xing Zheng <zhengxing@rock-chips.com> - 2016-01-10 08:30 +0100
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