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[PATCH 4/9] clk: tegra: Fix the misnaming of nvenc from msenc

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When adding the nvenc clock, it was partially named msenc in
the code. Since the msenc clk isn't present in T210 where the nvenc
clk is, its misleading to see it present. Therefore, properly
rename it.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
---
 drivers/clk/tegra/clk-tegra-periph.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 105405ca85ab..1860df1862dd 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -773,7 +773,7 @@ static struct tegra_periph_init_data periph_clks[] = {
 	XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
 	XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src_8),
 	MUX8("dbgapb", mux_pllp_clkm_2, CLK_SOURCE_DBGAPB, 185, TEGRA_PERIPH_NO_RESET, tegra_clk_dbgapb),
-	MUX8("msenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
+	MUX8("nvenc", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVENC, 219, 0, tegra_clk_nvenc),
 	MUX8("nvdec", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVDEC, 194, 0, tegra_clk_nvdec),
 	MUX8("nvjpg", mux_pllc2_c_c3_pllp_plla1_clkm, CLK_SOURCE_NVJPG, 195, 0, tegra_clk_nvjpg),
 	MUX8("ape", mux_plla_pllc4_out0_pllc_pllc4_out1_pllp_pllc4_out2_clkm, CLK_SOURCE_APE, 198, TEGRA_PERIPH_ON_APB, tegra_clk_ape),
-- 
1.9.1

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[PATCH 0/9 REPOST] Tegra CLK Fixes Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 4/9] clk: tegra: Fix the misnaming of nvenc from msenc Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 3/9] clk: tegra210: Fix naming of MISC registers Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 2/9] clk: tegra210: Remove improper flags for lock_enable Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 6/9] clk: tegra210: fix pllx dyn step calculation Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 7/9] clk: tegra: pll: Do not disable PLLE when under HW control Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
    Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Thierry Reding <thierry.reding@gmail.com> - 2016-01-13 15:10 +0100
      Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein <rklein@nvidia.com> - 2016-01-13 17:30 +0100
        Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Thierry Reding <thierry.reding@gmail.com> - 2016-01-13 18:30 +0100
  [PATCH 1/9] clk: tegra: Fix divider on VI_I2C Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  Re: [PATCH 0/9 REPOST] Tegra CLK Fixes Thierry Reding <thierry.reding@gmail.com> - 2016-01-13 15:10 +0100

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