Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate

From	Thierry Reding <thierry.reding@gmail.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate
Date	2016-01-13 15:10 +0100
Message-ID	<qQuhA-Oj-9@gated-at.bofh.it> (permalink)
References	<qOKgN-2ix-11@gated-at.bofh.it> <qOKgO-2ix-31@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Fri, Jan 08, 2016 at 01:45:14PM -0500, Rhyland Klein wrote:
> Initialize PLL_D2 to a sane rate at the start of the day.
> 
> Signed-off-by: Rhyland Klein <rklein@nvidia.com>
> ---
>  drivers/clk/tegra/clk-tegra210.c | 1 +
>  1 file changed, 1 insertion(+)

There are a lot of assumptions in this commit message. I'm asking myself
why does it need to be initialized to any rate at all? Isn't it up to
the user driver to set the PLL to whatever it knows to be a sane rate?
Why is 594 MHz a sane rate?

A good commit message should answer those questions.

Thierry

Thread

[PATCH 0/9 REPOST] Tegra CLK Fixes Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 4/9] clk: tegra: Fix the misnaming of nvenc from msenc Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 3/9] clk: tegra210: Fix naming of MISC registers Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 2/9] clk: tegra210: Remove improper flags for lock_enable Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 6/9] clk: tegra210: fix pllx dyn step calculation Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 7/9] clk: tegra: pll: Do not disable PLLE when under HW control Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
    Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Thierry Reding <thierry.reding@gmail.com> - 2016-01-13 15:10 +0100
      Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein <rklein@nvidia.com> - 2016-01-13 17:30 +0100
        Re: [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Thierry Reding <thierry.reding@gmail.com> - 2016-01-13 18:30 +0100
  [PATCH 1/9] clk: tegra: Fix divider on VI_I2C Rhyland Klein <rklein@nvidia.com> - 2016-01-08 19:50 +0100
  Re: [PATCH 0/9 REPOST] Tegra CLK Fixes Thierry Reding <thierry.reding@gmail.com> - 2016-01-13 15:10 +0100

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