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[PATCH V4 08/16] soc: tegra: pmc: Fix checking of valid partitions

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The tegra power partitions are referenced by a numerical ID which are
the same values programmed into the PMC registers for controlling the
partition. For a given device, the valid partition IDs may not be
contiguous and so simply checking that an ID is not greater than the
maximum ID supported may not mean it is valid. Fix this by computing
a bit-mask of the valid partition IDs for a device and add a macro that
will test if the partition is valid based upon this mask.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
 drivers/soc/tegra/pmc.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 28d3106d3add..0967bba13947 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -103,6 +103,7 @@
 #define GPU_RG_CNTRL			0x2d4
 
 #define PMC_PWRGATE_STATE(status, id)	((status & BIT(id)) != 0)
+#define PMC_PWRGATE_IS_VALID(id)	(pmc->powergates_mask & BIT(id))
 
 struct tegra_pmc_soc {
 	unsigned int num_powergates;
@@ -134,6 +135,7 @@ struct tegra_pmc_soc {
  * @cpu_pwr_good_en: CPU power good signal is enabled
  * @lp0_vec_phys: physical base address of the LP0 warm boot code
  * @lp0_vec_size: size of the LP0 warm boot code
+ * @powergates_mask: Bit mask of valid power gates
  * @powergates_lock: mutex for power gate register access
  */
 struct tegra_pmc {
@@ -158,6 +160,7 @@ struct tegra_pmc {
 	bool cpu_pwr_good_en;
 	u32 lp0_vec_phys;
 	u32 lp0_vec_size;
+	u32 powergates_mask;
 
 	struct mutex powergates_lock;
 };
@@ -213,7 +216,7 @@ static int tegra_powergate_set(int id, bool new_state)
  */
 int tegra_powergate_power_on(int id)
 {
-	if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
+	if (!PMC_PWRGATE_IS_VALID(id))
 		return -EINVAL;
 
 	return tegra_powergate_set(id, true);
@@ -225,7 +228,7 @@ int tegra_powergate_power_on(int id)
  */
 int tegra_powergate_power_off(int id)
 {
-	if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
+	if (!PMC_PWRGATE_IS_VALID(id))
 		return -EINVAL;
 
 	return tegra_powergate_set(id, false);
@@ -240,7 +243,7 @@ int tegra_powergate_is_powered(int id)
 {
 	u32 status;
 
-	if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
+	if (!PMC_PWRGATE_IS_VALID(id))
 		return -EINVAL;
 
 	status = tegra_pmc_readl(PWRGATE_STATUS);
@@ -256,7 +259,7 @@ int tegra_powergate_remove_clamping(int id)
 {
 	u32 mask;
 
-	if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates)
+	if (!PMC_PWRGATE_IS_VALID(id))
 		return -EINVAL;
 
 	/*
@@ -1084,7 +1087,7 @@ static int __init tegra_pmc_early_init(void)
 	struct device_node *np;
 	struct resource regs;
 	bool invert;
-	u32 value;
+	u32 value, i;
 
 	np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
 	if (!np) {
@@ -1136,6 +1139,11 @@ static int __init tegra_pmc_early_init(void)
 		return -ENXIO;
 	}
 
+	/* Create a bit-mask of the valid partitions */
+	for (i = 0; i < pmc->soc->num_powergates; i++)
+		if (pmc->soc->powergates[i])
+			pmc->powergates_mask |= BIT(i);
+
 	mutex_init(&pmc->powergates_lock);
 
 	/*
-- 
2.1.4

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Thread

[PATCH V4 00/16] Add generic PM domain support for Tegra Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 02/16] soc: tegra: pmc: Add missing structure members to kernel-doc Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 12/16] Documentation: DT: bindings: Add power domain info for NVIDIA PMC Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
    Re: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain  info for NVIDIA PMC Rob Herring <robh@kernel.org> - 2015-12-06 01:40 +0100
      Re: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain  info for NVIDIA PMC Jon Hunter <jonathanh@nvidia.com> - 2015-12-07 11:00 +0100
    Re: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain info for NVIDIA PMC Kevin Hilman <khilman@kernel.org> - 2015-12-08 20:10 +0100
      Re: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain  info for NVIDIA PMC Jon Hunter <jonathanh@nvidia.com> - 2015-12-09 13:30 +0100
        Re: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain  info for NVIDIA PMC Jon Hunter <jonathanh@nvidia.com> - 2015-12-09 13:40 +0100
  [PATCH V4 07/16] soc: tegra: pmc: Remove non-existing power partitions for T210 Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 06/16] soc: tegra: pmc: Wait for powergate state to change Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 05/16] soc: tegra: pmc: Avoid extra remapping of PMC registers Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 10/16] PM / Domains: Add function to remove a pm-domain Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 16/16] ARM64: tegra: select PM_GENERIC_DOMAINS Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 13/16] soc: tegra: pmc: Add generic PM domain support Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 08/16] soc: tegra: pmc: Fix checking of valid partitions Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 01/16] reset: add of_reset_control_get_by_index() Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100

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