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[PATCH V4 12/16] Documentation: DT: bindings: Add power domain info for NVIDIA PMC

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Add power-domain binding documentation for the NVIDIA PMC driver in
order to support generic power-domains.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>

---

Please note that I have been debating whether I add this
"nvidia,powergate-clock-disable" property or just leave the clocks
disabled by default. Some downstream kernels leave the clocks enabled
for the audio power-domain because the clocks required for powering up
the power-domain are needed by all modules within the power-domain.
However are the same time there are other power-domains that may need
to be on, but not always clocked and so having the ability to specify if
the clocks should be disabled seems useful. However, I can also remove
this and just have the appropriate devices turn on the clocks as well.
---
 .../bindings/arm/tegra/nvidia,tegra20-pmc.txt      | 61 ++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
index 838e1a69ec0a..8e4641db51a9 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt
@@ -1,5 +1,7 @@
 NVIDIA Tegra Power Management Controller (PMC)
 
+== Power Management Controller Node ==
+
 The PMC block interacts with an external Power Management Unit. The PMC
 mostly controls the entry and exit of the system from different sleep
 modes. It provides power-gating controllers for SoC and CPU power-islands.
@@ -69,6 +71,10 @@ Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip'
                      Defaults to 0. Valid values are described in section 12.5.2
                      "Pinmux Support" of the Tegra4 Technical Reference Manual.
 
+Optional nodes:
+- pm-domains : This node contains a hierarchy of PM domain nodes, which should
+	       match the power-domains on the Tegra SoC.
+
 Example:
 
 / SoC dts including file
@@ -114,3 +120,58 @@ pmc@7000f400 {
 	};
 	...
 };
+
+
+== PM Domain Nodes ==
+
+Each of the PM domain nodes represents a power-domain on the Tegra SoC
+that can be power-gated by the PMC and should be named appropriately.
+
+Required properties:
+  - clocks: Must contain an entry for each clock required by the PMC for
+    controlling a power-gate. See ../clocks/clock-bindings.txt for details.
+  - resets: Must contain an entry for each reset required by the PMC for
+    controlling a power-gate. See ../reset/reset.txt for details.
+  - nvidia,powergate: Integer cell that contains an identifier for the PMC
+    power-gate that is associated with the power-domain. Please refer to
+    the Tegra TRM for more details.
+  - #power-domain-cells: Must be 0.
+
+Optional properties:
+  - nvidia,powergate-disable-clocks: Boolean property that if present
+    indicates that the clocks listed in the "clocks" property should be
+    disabled after turning on the power-domain. Otherwise the clocks will
+    be kept enabled.
+
+Example:
+
+	pmc: pmc@0,7000e400 {
+		compatible = "nvidia,tegra210-pmc";
+		reg = <0x0 0x7000e400 0x0 0x400>;
+		clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
+		clock-names = "pclk", "clk32k_in";
+
+		pm-domains {
+			pd_audio: aud {
+				clocks = <&tegra_car TEGRA210_CLK_APE>,
+					 <&tegra_car TEGRA210_CLK_APB2APE>;
+				resets = <&tegra_car 198>;
+				nvidia,powergate = <TEGRA_POWERGATE_AUD>;
+				#power-domain-cells = <0>;
+			};
+		};
+	};
+
+
+== PM Domain Consumers ==
+
+Hardware blocks belonging to a PM domain should contain a "power-domains"
+property that is a phandle pointing to the corresponding PM domain node.
+
+Example:
+
+	adma: adma@702e2000 {
+		...
+		power-domains = <&pd_audio>;
+		...
+	};
-- 
2.1.4

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Thread

[PATCH V4 00/16] Add generic PM domain support for Tegra Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 02/16] soc: tegra: pmc: Add missing structure members to kernel-doc Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 12/16] Documentation: DT: bindings: Add power domain info for NVIDIA PMC Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
    Re: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain  info for NVIDIA PMC Rob Herring <robh@kernel.org> - 2015-12-06 01:40 +0100
      Re: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain  info for NVIDIA PMC Jon Hunter <jonathanh@nvidia.com> - 2015-12-07 11:00 +0100
    Re: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain info for NVIDIA PMC Kevin Hilman <khilman@kernel.org> - 2015-12-08 20:10 +0100
      Re: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain  info for NVIDIA PMC Jon Hunter <jonathanh@nvidia.com> - 2015-12-09 13:30 +0100
        Re: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain  info for NVIDIA PMC Jon Hunter <jonathanh@nvidia.com> - 2015-12-09 13:40 +0100
  [PATCH V4 07/16] soc: tegra: pmc: Remove non-existing power partitions for T210 Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 06/16] soc: tegra: pmc: Wait for powergate state to change Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 05/16] soc: tegra: pmc: Avoid extra remapping of PMC registers Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 10/16] PM / Domains: Add function to remove a pm-domain Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 16/16] ARM64: tegra: select PM_GENERIC_DOMAINS Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 13/16] soc: tegra: pmc: Add generic PM domain support Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 08/16] soc: tegra: pmc: Fix checking of valid partitions Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100
  [PATCH V4 01/16] reset: add of_reset_control_get_by_index() Jon Hunter <jonathanh@nvidia.com> - 2015-12-04 16:10 +0100

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