Groups > sci.electronics.design > #454464

Re: Identification of modules

From	Piotr Wyderski <peter.pan@neverland.mil>
Newsgroups	sci.electronics.design
Subject	Re: Identification of modules
Date	2017-03-31 22:14 +0200
Organization	ATMAN - ATM S.A.
Message-ID	<obmdcf$3er$1@node1.news.atman.pl> (permalink)
References	(1 earlier) <obl6rb$kvi$1@dont-email.me> <obl8v7$sps$1@node1.news.atman.pl> <obla43$v8b$1@dont-email.me> <oblbl2$via$1@node1.news.atman.pl> <obm3db$mmh$1@dont-email.me>

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rickman wrote:

> 2 dedicated signals per slot is simple but 3 isn't?

3 signals from each slot will need to be interleaved
on the PCB, while 2 make non-interleaved busses.

 > I believe you said somewhere else that the 2 are already used
 > for other functions.  How will the analog voltage get into the card?

 From above, through holes drilled in an appropriate place
to connect two THT resistors.

https://postimg.org/image/ligbk01nl/

This is what I consider simple. 2 busses on the edges
of the connectors, common signals in the middle, the
slot ID resistor dividers connected to pins 5.

> You haven't said *where* the CPUs are.

Technically, on a special module, they have their dedicated
connectors on the backplane and drive the lines from the image above.

>  There are lots of things you haven't explained about your
> system.  It's hard to suggest solutions when the system is not defined
> fully.

What would you like to be better defined, Rick?
The backplane is a row of straight 20-gold pin connectors,
the modules are to be installed vertically.

	Best regards, Piotr

Thread

Identification of modules Piotr Wyderski <peter.pan@neverland.mil> - 2017-03-31 09:21 +0200
  Re: Identification of modules Don Y <blockedofcourse@foo.invalid> - 2017-03-31 01:31 -0700
    Re: Identification of modules Piotr Wyderski <peter.pan@neverland.mil> - 2017-03-31 10:36 +0200
      Re: Identification of modules Don Y <blockedofcourse@foo.invalid> - 2017-03-31 02:16 -0700
        Re: Identification of modules Piotr Wyderski <peter.pan@neverland.mil> - 2017-03-31 11:39 +0200
          Re: Identification of modules Tom Gardner <spamjunk@blueyonder.co.uk> - 2017-03-31 11:32 +0100
            Re: Identification of modules Piotr Wyderski <peter.pan@neverland.mil> - 2017-03-31 12:59 +0200
          Re: Identification of modules Don Y <blockedofcourse@foo.invalid> - 2017-03-31 11:55 -0700
    Re: Identification of modules Piotr Wyderski <peter.pan@neverland.mil> - 2017-03-31 11:30 +0200
  Re: Identification of modules rickman <gnuarm@gmail.com> - 2017-03-31 05:20 -0400
    Re: Identification of modules Piotr Wyderski <peter.pan@neverland.mil> - 2017-03-31 11:53 +0200
      Re: Identification of modules rickman <gnuarm@gmail.com> - 2017-03-31 06:16 -0400
        Re: Identification of modules Piotr Wyderski <peter.pan@neverland.mil> - 2017-03-31 12:39 +0200
          Re: Identification of modules rickman <gnuarm@gmail.com> - 2017-03-31 13:27 -0400
            Re: Identification of modules Piotr Wyderski <peter.pan@neverland.mil> - 2017-03-31 22:14 +0200
              Re: Identification of modules rickman <gnuarm@gmail.com> - 2017-03-31 17:48 -0400
                Re: Identification of modules Piotr Wyderski <peter.pan@neverland.mil> - 2017-04-03 10:57 +0200
    Re: Identification of modules John Devereux <john@devereux.me.uk> - 2017-03-31 11:39 +0100
      Re: Identification of modules rickman <gnuarm@gmail.com> - 2017-03-31 13:38 -0400
        Re: Identification of modules Piotr Wyderski <peter.pan@neverland.mil> - 2017-03-31 22:21 +0200
  Re: Identification of modules Joe Chisolm <jchisolm6@earthlink.net> - 2017-03-31 13:02 -0500
  Re: Identification of modules Tim Wescott <seemywebsite@myfooter.really> - 2017-03-31 16:18 -0500

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