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Groups > comp.lang.forth > #50979
| From | rickman <gnuarm@gmail.com> |
|---|---|
| Newsgroups | comp.lang.forth |
| Subject | Re: OKAD? |
| Date | 2016-09-14 17:20 -0400 |
| Organization | A noiseless patient Spider |
| Message-ID | <nrcev8$dn4$1@dont-email.me> (permalink) |
| References | (14 earlier) <20160914103350.6ef344c2@HP-6550b> <nrb6q6$o3f$1@dont-email.me> <20160914113338.42e4566d@HP-6550b> <nrc0pn$of6$1@dont-email.me> <20160914210231.2024c373@HP-6550b> |
On 9/14/2016 4:02 PM, Jan Coombs wrote: > On Wed, 14 Sep 2016 13:18:48 -0400 > rickman <gnuarm@gmail.com> wrote: > >> On 9/14/2016 6:33 AM, Jan Coombs wrote: >>> On Wed, 14 Sep 2016 05:55:20 -0400 >>> rickman <gnuarm@gmail.com> wrote: >>> >>>> On 9/14/2016 5:33 AM, Jan Coombs wrote: >>>>> On Wed, 14 Sep 2016 05:08:52 -0400 >>>>> rickman <gnuarm@gmail.com> wrote: >>>>> >>>>>> Some people insist in referring to the delay line >>>>>> technique as a "ring oscillator". >>>>> >>>>> Maybe Chucks ring oscillator has both taps and gating, and >>>>> is the only delay element in each processor core? >>>> >>>> Except that it doesn't oscillate. When the CPU is waiting >>>> it stops. >>> >>> If you have gates in the ring oscillator loop you can pause >>> or stop the clock at any phase. >>> >>> Chuck must have at least one gate to be able to pause it. >> >> I don't get why you feel it has to be a "ring oscillator". >> There are many different timings each one adjusted to match >> the circuit it is timing. > > I like your ASCIIart, but cannot quickly see how it affects the > operation cycle of a S40C18 or similar processor. > > Perhaps we should build a model in HDL with realistic gate > delays and see if we can guess any closer, or even reproduce > the instruction timing as in the data sheet. > > I think that it might be possible to model asynchronous logic on > ProASIC3 and similar parts, so the library components for these > might be a practical starting point if we hoped to reproduce > anything close to Chuck's work. If that diagram does not mean anything to you, we are mis-communicating at a fundamental level and coding would not help. I have not read about the processor in the S40C18 in any detail, but it appears similar to the processor in the GA144. I believe the diagram you snipped is a useful block diagram of the functionality. I know that processor has different instruction timing for different categories of instructions. That is why I show different timing circuits. The control circuit selects a delay circuit based on the opcode being executed. Some instructions are simple, requiring a minimum delay. But with multiple instructions per instruction word, there is a timer for the next instruction word prefetch. If a branch occurs in the instruction word a different timer must be selected. If a memory instruction is executed a different timer is selected. If an I/O instruction is executed a different timer is selected and control may also depend on a signal back from the I/O unit. The processor is typically stopped until the I/O operation is complete which requires a response from the neighbor. I get the impression you are thinking of other types of asynchronous logic where the timing information is contained within the data path itself. I am pretty sure that is not how the GA144 operates, but I can't say for certain of course. -- Rick C
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OKAD? Mux <Yvo.Zoer@gmail.com> - 2016-08-22 15:07 -0700
Re: OKAD? Paul Rubin <no.email@nospam.invalid> - 2016-08-22 15:31 -0700
Re: OKAD? Bernd Linsel <bl1@gmx.com> - 2016-08-23 01:45 +0200
Re: OKAD? Mux <Yvo.Zoer@gmail.com> - 2016-08-23 13:55 -0700
Re: OKAD? JUERGEN <epldfpga@aol.com> - 2016-09-09 00:18 -0700
Re: OKAD? JUERGEN <epldfpga@aol.com> - 2016-09-09 02:47 -0700
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-09 11:52 -0400
Re: OKAD? JUERGEN <epldfpga@aol.com> - 2016-09-09 10:22 -0700
Re: OKAD? Mark Wills <markwills1970@gmail.com> - 2016-09-09 14:57 -0700
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-09 18:02 -0400
Re: OKAD? Paul Rubin <no.email@nospam.invalid> - 2016-09-09 15:33 -0700
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-10 01:55 -0400
Re: OKAD? mhx@iae.nl - 2016-09-09 23:36 -0700
Re: OKAD? Jecel <jecel@merlintec.com> - 2016-09-12 13:48 -0700
Re: OKAD? Paul Rubin <no.email@nospam.invalid> - 2016-09-12 14:17 -0700
Re: OKAD? Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-09-13 00:01 +0100
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-13 14:54 -0400
Re: OKAD? Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-09-14 08:50 +0100
Re: OKAD? Paul Rubin <no.email@nospam.invalid> - 2016-09-14 01:15 -0700
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-14 05:08 -0400
Re: OKAD? Paul Rubin <no.email@nospam.invalid> - 2016-09-14 02:14 -0700
Re: OKAD? Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-09-14 10:33 +0100
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-14 05:55 -0400
Re: OKAD? Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-09-14 11:33 +0100
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-14 13:18 -0400
Re: OKAD? Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-09-14 21:02 +0100
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-14 17:20 -0400
Re: OKAD? Jecel <jecel@merlintec.com> - 2016-09-15 10:54 -0700
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-15 17:28 -0400
Re: OKAD? Jecel <jecel@merlintec.com> - 2016-09-16 10:38 -0700
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-17 17:05 -0400
Re: OKAD? Jecel <jecel@merlintec.com> - 2016-09-21 13:42 -0700
Re: OKAD? rickman <gnuarm@gmail.com> - 2016-09-21 18:03 -0400
Re: OKAD? Jecel <jecel@merlintec.com> - 2016-09-23 13:21 -0700
Re: OKAD? albert@cherry.spenarnc.xs4all.nl (Albert van der Horst) - 2016-09-09 14:01 +0200
Re: OKAD? JUERGEN <epldfpga@aol.com> - 2016-09-09 04:57 -0700
Re: OKAD? Ilya Tarasov <ilya74.tarasov@gmail.com> - 2016-09-13 09:18 -0700
Re: OKAD? JUERGEN <epldfpga@aol.com> - 2016-09-13 10:09 -0700
Re: OKAD? Ilya Tarasov <ilya74.tarasov@gmail.com> - 2016-09-16 17:24 -0700
Re: OKAD? JUERGEN <epldfpga@aol.com> - 2016-09-17 02:38 -0700
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