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Re: PCI-enum and SouthBridge behaviour...

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James Harris wrote:

>> my ranting about missing PCI devices when I boot from SATA:

>> its again (remember my issues with boot from CD) a morphing BIOS story.
>> I couldn't figure why it behaves different, but it does.

>> my old (working since 2004) code use only PCI-mechanism 01 (via port
>> pair 0xcf8/0cfc) for PCI scan.
 
> According to my PCI book that has been THE way to access PCI 
> configuration since at least PCI 2.2.
 
> There was an older way, via two byte-wide ports at 0xcf8/0xcfa.
 
> But neither would work on machines which do not have an IO space. They 
> would have to use memory mapping. Are you saying, below, that you are 
> using memory mapping to do PCI configuration? If so, how do you begin 
> the process, e.g. to find out where the PCI devices are mapped?

Yes, and I get it from "MMIO Configuration Base Address Register" 
this is MSR C001_0058 on AMD CPUs (dont know where Intel have it).

>> So when I boot from SATA the BIOS use PCI-mech 02 (IOMM) starting at
>> 0xE000_0000 but I still have no idea why devices/functions arent
>> visible with PCI-mech 01 as well.
>> Finally I'll change my code to check if IOMM is available and use it.
 
> So you get full results from memory mapped PCI config, even when you 
> boot from SATA? 

Yes, all devices and functions are visible and easier accessible too.

> But on SATA boot IO-based config hides some devices? 

unfortunately yes, it could be a bug or something I havent figured yet. 
__
wolfgang 

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PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-22 21:53 +0200
  Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-24 16:52 +0100
    Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-24 19:54 +0200
      Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-25 07:07 +0100
        Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-25 11:04 +0200
          Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-25 10:30 +0100
            Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-25 14:06 +0200
              Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-25 13:16 +0100
                Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-26 13:09 +0200
                Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-26 15:14 +0100
          Re: PCI-enum and SouthBridge behaviour... Rod Pemberton <NoHaveNotOne@bcczxcfrze.cam> - 2016-07-25 21:55 -0400
            Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-26 12:48 +0200
  Re: PCI-enum and SouthBridge behaviour... Rod Pemberton <NoHaveNotOne@bcczxcfrze.cam> - 2016-07-26 08:18 -0400
    Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-26 20:11 +0200
  Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-28 18:53 +0200
    Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-29 19:47 +0200
      Re: PCI-enum and SouthBridge behaviour... Rod Pemberton <NoHaveNotOne@zxdehrnyya.cam> - 2016-07-29 17:44 -0400
        Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-30 09:44 +0200
    Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-30 12:55 +0100
      Re: PCI-enum and SouthBridge behaviour... "wolfgang kern" <nowhere@never.at> - 2016-07-30 19:40 +0200
        Re: PCI-enum and SouthBridge behaviour... James Harris <james.harris.1@gmail.com> - 2016-07-30 19:08 +0100

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