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Re: Forth in VHDL

Cross-posted to 2 groups.

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On 7/26/2016 12:00 PM, Anton Ertl wrote:
> rickman <gnuarm@gmail.com> writes:
>> I have been
>> told the clock tree in a large chip can dissipate half the power.
>
> IIRC the clock for the 21064 (1992) consumed 30% of the power, and the
> final driver of the clock had a gate length of 35cm.  That was at
> 200MHz.
>
> Of course that could not scale, so quite some time ago they have
> divided the chips into smaller clock domains (and later also power
> domains); e.g., the Williamette (first Pentium 4, 2001, 1400MHz) had a
> very fast integer ALU core that, however, did not include
> multiplication or shifting.  So integer multiplication and shifting
> were achieved by shipping the data over to the FPU, and then shipping
> the result back.  The data had to cross several clock domain borders
> on the way, losing a cycle on every crossing; that's why integer
> multiplication is slower than FP multiplication on the Pentium 4.
>
>> The bottom line is asynchronously clocked CPU chips have been designed
>> before but have never made an impact on the market.  I recall one that
>> was an 8051 I believe and I seem to recall an ARM being designed this
>> way.  Of course, the GA144 is the most notable and possibly the most
>> successful example so far.
>
> AFAIK the GA144 is not an asynchronous design; it's a clocked design,
> but the clock is generated internally (one clock per core).  At least
> an earlier chip by Chuck Moore worked that way (IIRC the MuP21), and
> the idea that this was an async design was already rampant (and
> contradicted) at the time.

None of the CPUs described as "asynchronous" are truly that.  They are 
asynchronously clocked.  In the GA144 there are delay paths that are 
activated for each type of instruction with a delay matched to the time 
taken for that class of instruction.  Someone here argued with me that 
this constituted an astable oscillator but that is just semantics.  Of 
course it will oscillate as the end of any one clock period has to 
coincide with the beginning of the next.  But just like all the other 
"async" CPUs, the GA144 is async in the same way, asynchronously clocked.

True asynchronous logic is different.  It has no clocked registers.  The 
logic is self latching like RS FFs and has to be designed very 
differently even from asynchronously clocked logic.  I remember an async 
logic state machine available many years ago when PLDs were still new. 
It was true async logic, but never made much of a dent in the market.  I 
saw it used on one design which likely became out of date due to the 
part becoming obsolete not too long after.

-- 

Rick C

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Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 22:29 -0400
  Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:01 -0400
    Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:05 -0400
      Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 22:25 -0500
        Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 00:08 -0400
          Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 23:57 -0500
            Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:22 -0400
              Re: Forth in VHDL Paul Rubin <no.email@nospam.invalid> - 2016-07-24 22:38 -0700
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:53 -0400
              Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 14:11 -0500
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 17:39 -0400
                Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 18:01 -0500
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 19:40 -0400
                Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-26 11:04 +0100
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 11:13 -0400
                Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-26 16:00 +0000
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 12:58 -0400
                Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-27 09:39 +0000
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 10:01 -0400
                Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-27 22:46 +0100
    Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 18:15 -0400

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