Re: Forth in VHDL

From	Jan Coombs <jenfhaomndgfwutc@murmic.plus.com>
Newsgroups	comp.lang.vhdl, comp.lang.forth
Subject	Re: Forth in VHDL
Date	2016-07-26 11:04 +0100
Organization	A noiseless patient Spider
Message-ID	<20160726110441.73da10eb@HP-6550b> (permalink)
References	(3 earlier) <nn40r6$o88$1@dont-email.me> <nn43co$tha$1@dont-email.me> <nn468n$3k2$1@dont-email.me> <nn47lq$6r4$1@dont-email.me> <nn5o8m$6v0$1@dont-email.me>

Cross-posted to 2 groups.

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On Mon, 25 Jul 2016 14:11:16 -0500
Cecil Bayona <cbayona@cbayona.com> wrote:

> On 7/25/2016 12:22 AM, rickman wrote:

> > You really can't design async logic in FPGAs that I know
> > of.  It has to be custom chips.  Achronix is developing
> > async logic FPGAs, but I think they are intent on the really
> > big customers only, small users need not apply.
> 
> I have not looked into it but you might be right as the LUTS
> have flip flops on their outputs and would need to be clocked.

Yes, if a logic device uses LUTs, then it needs to latch the LUT
output when it is stable, and the longest logic propagation time
must fit between two clock edges. 

In the fine-grained Microsemi/Actel Flash FPGAs there are no
LUTs, the programmable element is either logic or a flop. There
are only eight synchronous library parts, and the majority of
the rest are purely combinatorial.  [1]

Perhaps these parts could be used to synthesize async logic
designs.   

Jan Coombs
-- 
[1] IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide
http://www.microsemi.com/document-portal/doc_view/130886-igloo-proasic3-smartfusion-and-fusion-macro-library-guide-for-software-v9-0
[2] https://en.wikipedia.org/wiki/Asynchronous_circuit

Thread

Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 22:29 -0400
  Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:01 -0400
    Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-24 23:05 -0400
      Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 22:25 -0500
        Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 00:08 -0400
          Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-24 23:57 -0500
            Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:22 -0400
              Re: Forth in VHDL Paul Rubin <no.email@nospam.invalid> - 2016-07-24 22:38 -0700
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 01:53 -0400
              Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 14:11 -0500
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 17:39 -0400
                Re: Forth in VHDL Cecil Bayona <cbayona@cbayona.com> - 2016-07-25 18:01 -0500
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-25 19:40 -0400
                Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-26 11:04 +0100
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 11:13 -0400
                Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-26 16:00 +0000
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-26 12:58 -0400
                Re: Forth in VHDL anton@mips.complang.tuwien.ac.at (Anton Ertl) - 2016-07-27 09:39 +0000
                Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 10:01 -0400
                Re: Forth in VHDL Jan Coombs <jenfhaomndgfwutc@murmic.plus.com> - 2016-07-27 22:46 +0100
    Re: Forth in VHDL rickman <gnuarm@gmail.com> - 2016-07-27 18:15 -0400

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